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전자부품 반도체 검색엔진( 무료 PDF 다운로드 ) - 데이터시트뱅크

OP221GS(RevA) 데이터 시트보기 (PDF) - Analog Devices

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OP221GS Datasheet PDF : 12 Pages
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OP221–SPECIFICATIONS (Matching Characteristics at Vs = ؎15 V, –55؇C TA +125؇C for OP221A,
–25؇C TA +85؇C for OP221E, –40؇C TA +85؇C for OP221G, unless otherwise noted.
Grades E and G are sample tested.)
.
OP221A/E
OP221G
Parameter
Symbol Conditions
Min Typ Max
Min Typ Max Unit
Input Offset
Voltage Match
VOS
Average Noninverting IB+
Bias Current
VCM = 0
100 400
100
400 800
µV
140 nA
Input Offset
Voltage Tracking
ICVOS
1
2
3
5
µV°C
Noninverting Input IOS+
Offset Current
VCM = 0
3
7
6
12
nA
Common-Mode
Rejection Ratio
Match (Note 1)
CMRR VCM = –15 V to 13.2 V
87
90
72
80
dB
Power Supply
Rejection Ratio
Match (Note 1)
PSRR
26
140 µV/V
NOTES
1CMRR is 20 log10 VCM/CME, where VCM is the voltage applied to both noninverting inputs and CME is the difference in common-mode input-referred error.
2PSRR is: Input-Referred Differential Error
VS
Wafer Test Limits at Vs = ؎2.5 V to ؎15 V, TA = 25؇C, unless otherwise noted.
.
Parameter
Symbol
Conditions
OP221N
Limit
Unit
Input Offset Voltage
VOS
200
µV Max
Input Offset Current
IOS
VCM = 0
3.5
nA Max
Input Bias Current
IB
VCM = 0
85
nA Max
Input Voltage Range
Common-Mode
Rejection Ratio
Power Supply
Rejection Ratio
IVR
CMRR
PSRR
V+ = 5 V, V– = 0 V
VS= ± 15 V
V– = 0 V, V+ = 5 V,
0 V VCM 3.5 V
VS = ± 15 V
–15 V VCM 13.5 V
VS = ± 2.5 V to ± 15 V
V– = 0 V, V+ = 5 V to 30 V
0/3.5
–15/13.5
88
93
12.5
22.5
V Min/Max
V Min
dB Min
V/mV Min
Large-Signal
Voltage Gain
Avo
VS = ± 15 V
RL = 10 k
1500
V/mV Max
Output Voltage Swing
VO
V+ = 5 V, V– = 0 V, RL= 10 k
VS = 15 V, RL = 10 k
0.7/4.1
± 13.8
V Min/Max
V Min
Supply Current
ISY
(Both Amplifiers)
VS = ± 2.5 V, No Load
VS = ± 15 V, No Load
560
µA Max
810
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
–4–
REV. A

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