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NTE7156

Integrated Circuit DC–Coupled Vertical Deflection Circuit

NTE Electronics 

Notes:

Note 1. A flyback supply voltage of > 50V up to 60V is allowed in application. A 22–nF capacititor

in series with a 22Ω resistor (depending on IO and the inductance of the coil) has to be con-

nected between Pin7 and GND. The decoupling capacitor of VFB has to be connected be-

tween Pin6 and Pin3. This supply voltage line must have a resistance of 33Ω.

Note 4. The linearity error is measured without S–correction and based on the same measurement

principle as performed on the screen. The measuring method is as follows:

Divide the output signal I4 – I7 (VRM) into 22 equal parts ranging from 1 to 22 inclusive. Measure

the value of two succeeding parts called one block starting with part 2 and 3 (block 1) and ending

with part 20 and 21 (block 10). Thus part 1 and 22 are unused. The equations for linearity error

for adjacent blocks (LEAB) and linearity error for not adjacent blocks (LENAB) are given below:

LEAB =

ak – a(k + 1)

aavg

Note 5. Referenced to VP.

; LEAB =

amax – amin

aavg

Note 6. The V values within formulae relate to voltages at or across relative pin numbers, i.e.

V7–4/V1–2 = voltage value across Pin7 and Pin4 divided by voltage value across Pin1 and Pin2.

Note 7. V9–4 AC short–circuited.

Note 8. Frequency response V7–4/V9–4 is equal to frequency response V7–4/V1–2.

Note 9. At V(ripple) = 500mV eff; measured across RM; fi = 50Hz.

Pin Connection Diagram

(Front View)

9 VI(fb)

8 VO(guard)

7 VO(A)

6 VFB

5 GND

4 VO(B)

3 VP

2 Idrive(neg)

1 Idrive(pos)

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