SPT7814(1991) 데이터 시트보기 (PDF) - Signal Processing Technologies

부품명

상세내역

일치하는 목록

SPT7814
(Rev.:1991)

AN7810/14 EVALUATION BOARD

Signal Processing Technologies 

The HDAC52160 was selected for the EB7810/14 (U12). It

is a 13-bit accurate device with ±0.012% FSR maximum DLE

and ±0.006 % FSR maximum ILE. The circuit shown in figure

8 can be used to interface with the EB7810/14 to visually

characterize the ILE and DLE. Because the DAC OUT signal

is opposite in phase with respect to the analog input, the

output of the circuit shown in figure 8 would be the quantiza-

tion error at the output of Ua. For a ramp analog input signal,

the quantization error will be as shown in figure 9.

R26 and R27 (EB7810/14) potentiometers are the

HDAC52160’s gain and offset adjustments, respectively.

Potentiometer Rb in figure 8 is the matching gain adjustment

between the analog input and the RECONSTRUCT signal.

These three potentiometers can be used to normalize two

end points and visually measure the ILE of the SPT7810 or

SPT7814 .

DYNAMIC TESTING

Figure 10 is the block diagram for dynamic testing of the

SPT7810 or SPT7814 using the EB7810/14 evaluation

board. In an earlier time, the DAC OUT signal had been used

to analyze the ADC’s dynamic performances (SNR and THD)

through a spectrum analyzer. This method of testing pre-

sented some uncertainties. The DAC must be near perfect,

free from glitches, and its dynamic accuracy (DLE and ILE)

must be far better than the ADC under test. Any errors in the

DAC would be added to the total SNR and/or THD.

Figure 10 - Dynamic Testing Test Set-Up

GENERATOR #1

REF

OUT SINEWAVE

(Fin)

GENERATOR #2

REF SINEWAVE

IN

(Fs)

GENERATOR #3

REF ECL

IN

(Fc)

BPF-1

BPF-2

VIN P1 /

P2

EB7810

CLK

IN

CCLK

HIGH SPEED

MEMORY

CPU / DSP

SCOPE OR

SPECTRUM

ANALYZER

by lowering the +5 V supply to approximately +4.7 V, or by

appropriately adding the series resistors to the digital inputs

of the HDAC52160.

In many cases, the speed of the capture memory is much

slower than the available output data of the ADC under test.

If this is the case, it is necessary to decimate the capture clock

at a rate of Fs / N, where N is a power of 2. The beat frequency

can be achieved by slightly changing the analog input fre-

quency by an amount of ∆fin. For a 4096-point FFT, the beat

frequency of ∆fin = Fc / 4096 would be added (or subtracted)

to the analog input frequency. 4096 data points will be filled

in one test period, where the input is at Fin ± (Fc/4096) and

the output is updated at 1/Fc interval. The selection of Fin is

suggested to be a multiple (integer) of Fc to achieve the

complete system synchronization.

Both capture memory and the DAC will run at a relatively low

update rate ( Fs / N), and the effect of the DAC glitches and

dynamic performances on the SNR will be minimized. In

addition, due to a relatively low update rate, a low bandwidth

spectrum analyzer can be used through the DAC measure-

ment.

EB7810/14 CALIBRATION

This section will serve as a guide for the calibration of the

EB7810/14. Verify that the following jumpers are installed :

J2, J4 and J5 (or J2, J3 and J6).

Equipment needed

• DC power supplies: +15 V, -15 V, +5 V and -5.2 V

• 2 Hewlett Packard, HP3325A, function generators,

or equivalent

• 1 Fluke 6060B, signal generator, or equivalent

• 1 DVM with 5&1/2 digit precision

• 1 Oscilloscope

Equipment set-up / hook-up

• Connect all 4 power supplies as shown in figure 2 and

figure 3.

Today, it is preferable to perform these tests by means of

digital signal processing (DSP). Presently, there are numer-

ous standard software packages on the market to service this

application. The EB7810/14 provides two data outputs to

accommodate an ECL or TTL interface (see table V and VI for

details). The DAC set-up can still be used as a coarse

measurement. Both set-ups are very important in character-

izing the dynamic performance of the SPT7810 or SPT7814

noting that, the EB7810/14 was not designed to optimize the

DAC glitch. The time skew from the ECL/TTL translator is

significant. An improvement of the DAC glitch can be made

• Follow figure 5 for the connection of the signal genera-

tors HP3325A for generator 1 and 3, and Fluke 6060A

for generator 2.

• Discard BPF-1 and BPF-2

Reference Calibration

Follow table II for the adjustment of Vcc, Vee, VST, VSB and

Vecl ( Note their respective monitoring test points and their

respective adjustment potentiometers).

SPT

AN7810/14

10

12/11/91

Share Link: