NJW1140 데이터 시트보기 (PDF) - Japan Radio Corporation
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NJW1140 Datasheet PDF : 15 Pages
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NJW1140
s DEFINITION OF I2C REGISTER
q I2C BUS FORMAT
MSB
LSB
MSB
LSB
MSB
S
Slave Address
A
Select Address
A
1bit
8bit
1bit
8bit
1bit
S: Starting Term
A: Acknowledge Bit
P: Ending Term
q SLAVE ADDRESS
MSB
1
0
0
0
0
0
1
Data
8bit
LSB
AP
1bit 1bit
LSB
R/W
R/W=0: Receive Only
q CONTROL REGISTER TABLE
The select address sets each function (Volume, Balance, AGC, Surround, Tone Control).
The auto increment function cycles the select address as follows.
00H¡01H¡02H¡03H¡04H¡05H¡00H
Select
BIT
Address
D7
D6
D5
D4
D3
00H
VOL
01H
CHS
BAL
02H
BCB
BASS
03H
BCT
TREB
04H
Don’t Care
05H
OUT
SEL
AGC1
q CONTROL REGISTER DEFAULT VALUE
D2
BCSB
BCST
AGC0
D1
D0
SR1
SR0
SUB-BASS
SUB-TREB
AGC Don’t Care
Select
BIT
Address
D7
D6
D5
D4
D3
D2
D1
D0
00H
0
0
0
0
0
0
0
0
01H
0
0
0
0
0
0
0
0
02H
0
0
0
0
0
0
0
0
03H
0
0
0
0
0
0
0
0
04H
0
0
0
0
0
0
0
0
05H
0
0
0
0
0
0
0
0
-7-
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