NJU6673CL 데이터 시트보기 (PDF) - Japan Radio Corporation

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NJU6673CL

25-common x 100-segment BITMAP LCD DRIVER

Japan Radio Corporation  

NJU6673

BLOCK DIAGRAM

Vss

VDD

V1 to V5

5

C1+

C1-

C2+

C2-

T1

T2

VR

C0

C14 S0

S99 C24

C15

COM

Driver

SEG

Driver

COM

Driver

Shift

Register

Shift

Register

Display Data Latch 100

Display Data RAM

100 x 25 bit

COM, SEG

Timing

Generator

CDIR

Column Address Decoder

Column Address Counter 8bit

Column Address Register 8bit

Multiplexer

Display

Timing

Generator

OSC.

Instruction

Decoder

Internal Bus

Status

BF Bus Holder

DUTY

OSC

Reset

RES

CPU interface

CS A0 RD WR SEL68 P/S

D0 to D5

D6(SCL)

D7(SI)

-6-

Ver.2003-04-08

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