NJU6356EM 데이터 시트보기 (PDF) - Japan Radio Corporation

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NJU6356EM

SERIAL I/O REAL TIME CLOCK

Japan Radio Corporation  

NJU6356

3. Timer Data Writing

When both of the I/O terminal and the CE terminal are "H", update is stopped, the oscillator divider is cleared,

and the timer data can be written to the NJU6356.

The timer data is written into the shift register from the DATA terminal by synchronized with rising edge of the

clock signal input from the CLK terminal, and the data is transferred from the shift register to the timer counter by

synchronized with falling edge of the CE signal. In this time the second-counter is cleared to "0", and the oscillator

divider start the operation.

The input data strings are LSB first of each digit as shown below.

Type E

Year

Month

Day

Days of

Week

Hour

Minute Second

The data is read out from LSB of Year, and last 44-bit is effective.

< Write Down Timing >

CLK

CE

I/O

Data

Input

Shift

Register

01 2 3 4 5 6 7

34567

Year

Minute

01 2 3 4 5 6 7

34567

The data is input into the shift

register at rising edge of the

CLK.

The data in the shift register is

transferred to the timer counter at this

falling edge of the CE, then the

oscillator divider start the operation.

Note) When the CE signal is which rising edge or falling edge,

the CLK signal should be fixed to "L". And so, before the

CE signal is raised, the I/O signal should be fixed to "H".

4. Low Voltage Detector

The NJU6356 series incorporate the low battery detector. If the supply voltage reduce to the detection level,

(EE)H is written into each digit of the shift register as warning code for the CPU.

5. Data Access

The NJU6356 series can operate from 2.0V to 5.5V. However, it is not allow the data access out of the range of

5V±10%. It may be broken the data unless 5V±10%.

Thus, when the data access, the CE terminal should be "H" after the power supply rise to 5V±10%, then start the

operation.

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