NCV8184 데이터 시트보기 (PDF) - ON Semiconductor
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NCV8184 Datasheet PDF : 13 Pages
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NCV8184
100
50% Duty Cycle
20%
10 10%
5%
2%
1 1%
Single Pulse
(1.0 in pad PCB) Die Size = 2.08 x 1.55 x 0.40 5.0% Active Area
0.1
0.000001 0.00001
0.0001
0.001
0.01
0.1
Notes:
PDM
t1
t2
t1
Duty Cycle, D = t 2
1
10
100
t1 (s)
Figure 30. DPAK 5−Lead Thermal Duty Cycle Curves on 1.0 in. Spreader Test Board
1000
1000
Die Size = 2.08 x 1.55 x 0.40 5.0% Active Area
100
min pad (Cu Area = 100 mm2)
10
1.0 in pad (Cu Area = 653 mm2)
1
0.1
0.000001
Junction
0.00001
0.0001
0.001
0.01
0.1
1
10
100
Time (s)
Figure 31. DPAK 5−Lead Thermal Transient Response on Typical Test Boards
R1
R2
R3
Rn
C1
C2
C3
Cn
1000
Time constants are not simple RC products.
Amplitudes of mathematical solution are not the resistance values.
Figure 32. Grounded Capacitor Thermal Network (“Cauer” Ladder)
Ambient
(thermal ground)
Junction
R1
R2
R3
Rn
C1
C2
C3
Cn
Each rung is exactly characterized by its RC−product time constant;
Amplitudes are the resistances
Ambient
(thermal ground)
Figure 33. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder)
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