datasheetbank_Logo
전자부품 반도체 검색엔진( 무료 PDF 다운로드 ) - 데이터시트뱅크

NCP5612 데이터 시트보기 (PDF) - ON Semiconductor

부품명
상세내역
일치하는 목록
NCP5612 Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
NCP5612
VBandGap
600 mV
LED Return
Pin 2 & 3
R1
GND
IREF Pin 4
GND
Note: the IREF pin must never be biased by an external voltage.
Figure 5. Basic Reference Current Source
Load Connection
The NCP5612 is capable to drive the two LED
simultaneously, as depicted (see Figure 1), but the load can
be arranged to accommodate one or two LED if necessary
in the application (see Figure 6). In this case, the two
current mirrors can be connected in parallel to drive a
single powerful LED, thus yielding 60 mA current
capability in a single LED.
NCP5612
NCP5612
7
7
LWY87S
D1 C4 1 mF/6.3 V
2
GND
3
LWY87S
D1
LWY87S
D2 C4
1 mF/6.3 V
2
GND
3
Figure 6. Typical Single and Double LED Connections
Finally, an external network can be connected across Vout
and ground, but the current through such network will not
be regulated by the NCP5612 chip (see Figure 7). On top
of that, the total current out of the Vout pin shall be limited
to 60 mA.
C4
NCP5612
7
1uF/6.3V
GND
LWY87S
D1
LWY87S
D3
LWY87S
20 mA
LWY87S
5mA
D2
2
20 mA
D4
5mA
R1
R2
220R
220R
3
GND
Figure 7. Extra Load Connected to Vout
Single Wire Serial Link Protocol
The proposed SWIRE uses a pulse count technique
already existing in the data exchange systems. The protocol
supports broken transmission, assuming the hold time is
shorter than the maximum 200 ms typical specified in the
data sheet. The SWIRE details are provided in the
AND8264 application note.
Based on the two examples provided in Figure 8, the
CNTL pin supports two digital level:
CNTL = Low ³ the system is shutoff and no current
flow in either LED1 or LED2.
CNTL = High ³ the system is active and the two LED
are powered according to the selected sequence.
There is no time delay associated with the Low state and
the LED are switched Off when the CNTL signal drops to
Low. To program a new LED configuration, one shall send
the number of pulses on the CNTL pin according to the true
table:
The internal counter is reset to zero on the first
negative going transient present on the CNTL pin
www.onsemi.com
7

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]