NCP361 데이터 시트보기 (PDF) - ON Semiconductor

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NCP361

USB Positive Overvoltage Protection Controller with Internal PMOS FET and Overcurrent Protection

ON Semiconductor 

NCP361, NCV361

Figure 22.

PCB Recommendations

The NCP361 integrates a 500 mA rated PMOS FET, and

the PCB rules must be respected to properly evacuate the

heat out of the silicon. The UDFN PAD1 must be connected

to ground plane to increase the heat transfer if necessary

from an application standpoint. Of course, in any case, this

pad shall be not connected to any other potential.

By increasing PCB area, the RqJA of the package can be

decreased, allowing higher charge current to fill the battery.

Taking into account that internal bondings (wires

between package and silicon) can handle up to 1 A (higher

than thermal capability), the following calculation shows

two different example of current capability, depending on

PCB area:

• With 305°C/W (without PCB area), allowing DC

current is 500 mA

• With 260°C/W (200 mm2), the charge DC current

allows with a 85°C ambient temperature is:

I = √(TJ-TA)/(RqJA x RDSON)

I = 625 mA

In every case, we recommend to make thermal

measurement on final application board to make sure of the

final Thermal Resistance.

380

50%

45%

330

40%

TSOP−5 1.0 oz

TSOP−5 2.0 oz

280

DFN 2x2.2 1.0 oz

DFN 2x2.2 2.0 oz

35%

% Delta DFN vs TSOP−5

30%

230

25%

20%

180

15%

10%

130

5%

80

0%

0

100

200

300

400

500

600

700

Copper heat spreader area (mm^2)

Figure 23. Thermal Resistance of UDFN 2x2 and TSOP Packages as a Function of PCB Area and Thickness

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