NCP1015 데이터 시트보기 (PDF) - ON Semiconductor
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NCP1015 Datasheet PDF : 22 Pages
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Tsw
Tstart
NCP1015
1 V Ripple
TLatch
Latch−off
Level
Figure 15. NCP1015 Facing a Fault Condition (Vin = 150 Vdc)
The rising slope from the latch−off level up to 8.5 V is
expressed by:
PDSS + Vin @ ICC1
tstart
+
DV1 @
IC1
C
The time during which the IC actually pulses is given by:
tsw
+
DV2 @ C
ICC1
Finally, the latch−off time can be derived using the same
formula topology:
tlatch
+
DV3 @ C
ICC2
From these three definitions, the burst duty−cycle D can
be computed:
D
+
tstart
)
tsw
tsw
)
tlatch
(eq. 2)
ǒ Ǔ D +
DV2
ICC1 @
DV2
ICC1
)
DV1
IC1
)
DV3
ICC2
(eq. 3)
Feeding the equation with values extracted from the
parameter section gives a typical duty−cycle D of 13%,
precluding any lethal thermal runaway while in a fault
condition.
DSS Internal Dissipation
The Dynamic Self−Supplied pulls the energy out from the
drain pin. In the Flyback−based converters, this drain level
can easily go above 600 V peak and thus increase the stress
on the DSS startup source. However, the drain voltage
evolves with time and its period is small compared to that of
the DSS. As a result, the averaged dissipation, excluding
capacitive losses, can be derived by:
PDSS + ICC1 @t VDS(t) u
(eq. 4)
Figure 16 shows a typical drain−ground wave−shape
where leakage effects have been removed:
Vds(t)
Vr
Vin
toff
dt
ton
t
Tsw
Figure 16. A Typical Drain−ground Waveshape
where Leakage Effects are Not Accounted for
By looking at Figure 16 the average result can easily be
derived by additive square area calculation:
t
VDS(t)
u+
Vin
@
(1
*
D)
)
Vr
@
toff
tsw
By developing Equation 5 we obtain:
(eq. 5)
t
VDS(t)
u+
Vin
*
Vin
@
ton
tsw
)
Vr
@
toff
tsw
toff can be expressed by:
(eq. 6)
toff
+
Ip
@
Lp
Vr
ton can be evaluated by:
(eq. 7)
ton
+
Ip
@
Lp
Vin
(eq. 8)
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