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NB100LVEP56 Datasheet PDF : 10 Pages
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NB100LVEP56
2.5V / 3.3V ECL DUAL
Differential 2:1 Multiplexer
Description
The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The
differential data path makes the device ideal for multiplexing low
skew clock or differential data signals. The device features both
individual and common select inputs to address both data path and
random logic applications. Common and individual selects can accept
both LVECL and LVCMOS input voltage levels. Multiple VBB pins
are provided.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended input operation, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Features
• Maximum Input Clock Frequency > 2.5 GHz Typical
• Maximum Input Data Rate > 2.5 Gb/s Typical
• 525 ps Typical Propagation Delays
• Low Profile QFN Package
• PECL Mode Operating Range:
VCC = 2.375 V to 3.8 V with VEE = 0 V
• NECL Mode Operating Range:
VCC = 0 V with VEE = −2.375 V to −3.8 V
• Separate, Common Select, and Individual Select
(Compatible with ECL and CMOS Input Voltage Levels)
• Q Output Will Default LOW with Inputs Open or at VEE
• Multiple VBB Outputs
• Pb−Free Packages are Available
http://onsemi.com
MARKING
DIAGRAMS*
TSSOP−20
DT SUFFIX
CASE 948E
24 1
24 PIN QFN
MN SUFFIX
CASE 485L
N100
VP56
ALYWG
G
24
1
N100
VP56
ALYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
November, 2006 − Rev. 9
Publication Order Number:
NB100LVEP56/D
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