HM5165165LTT-6 데이터 시트보기 (PDF) - Hitachi -> Renesas Electronics
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HM5165165LTT-6 Datasheet PDF : 36 Pages
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HM5164165 Series, HM5165165 Series
Operation Table
RAS LCAS UCAS WE OE I/O 0 to I/O 7 I/O 8 to I/O 15 Operation
H
×
×
×
×
High-Z
High-Z
Standby
L
L
H
H
L
Dout
High-Z
Read cycle
L
H
L
H
L
High-Z
Dout
L
L
L
H
L
Dout
Dout
L
L
H
L*2
×
Din
×
Early write cycle
L
H
L
L*2
×
×
Din
L
L
L
L*2
×
Din
Din
L
L
H
L*2
H
Din
×
Delayed write cycle
L
H
L
L*2
H
×
Din
L
L
L
L*2
H
Din
Din
L
L
H
H to L L to H Dout/Din
High-Z
Read-modify-write cycle
L
H
L
H to L L to H High-Z
Dout/Din
L
L
L
H to L L to H Dout/Din
Dout/Din
L
H
H
×
×
High-Z
High-Z
RAS-only refresh cycle
H to L H
L
H
×
High-Z
High-Z
CAS-before-RAS refresh cycle or
H to L L
H
H
×
High-Z
High-Z
Self refresh cycle (L-version)
H to L L
L
H
×
High-Z
High-Z
L
L
L
H
H
High-Z
High-Z
Read cycle (Output disabled)
Notes: 1. H: VIH (inactive) L: VIL (active) ×: VIH or VIL
2. tWCS ≥ 0 ns: Early write cycle
tWCS < 0 ns: Delayed write cycle
3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However
write operation and output High-Z control are done independently by each UCAS, LCAS.
ex. if RAS = H to L, LCAS = L, UCAS = H, then CAS-before-RAS refresh cycle is selected.
7
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