UD61464DC07 데이터 시트보기 (PDF) - Zentrum Mikroelektronik Dresden AG
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UD61464DC07 Datasheet PDF : 14 Pages
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UD61466
Dynamic Characteristics
3)
F ALL CYCLES
Transition Time (Rise and Fall)
4)
RAS Precharge Time
CAS Precharge Time
Row Address Set-up Time
Row Address Hold Time
Output Buffer Turn-off Delay Time
5)
Output Buffer Turn-off Delay Time from OE 5)
CAS to RAS Precharge Time
RAS to Column Address Delay Time
6)
Column Address to RAS Lead Time
CAS to Output in Low-Z
Refresh Period
F READ
Random Read Cycle Time
7)
Access Time from RAS
8)
Access Time from Column Address
8)
Access Time from CAS
8)
8)
OE Access Time
RAS Pulse Width
CAS Pulse Width
Read Command Set-up Time
Read Command Hold Time ref. to RAS
9)
Read Command Hold Time
9)
Column Address Hold Time ref. to RAS
10)
Column Address Hold Time ref. to RAS Rise
RAS to CAS Delay Time
6)
CAS Hold Time
RAS Hold Time
RAS Hold Time referenced to OE
Symbol
Alt.
IEC
Min.
Max.
Unit
DC07 DC08 DC07 DC08
tT
tt
3
3
50
50 ns
tRP
tw(RASH)
50
60
ns
tCP
tw(CASH)
10
10
ns
tASR
tsu(RA-RAS)
0
0
ns
tRAH
th(RAS-RA)
10
10
ns
tOFF
tOEZ
tv(CAS)
tv(G)
0
0
20
20 ns
0
0
20
20 ns
tCRP
tCASH-RASL
5
5
ns
tRAD
tRAS-CA
15
15
35
40 ns
tRAL
tCA-RASH
35
40
ns
tCLZ
tCASL-QX
0
0
ns
tREF
trf
4
4 ms
tRC
tRAC
tAA
tCAC
tOEA
tRAS
tCAS
tRCS
tRRH
tRCH
tAR
tAH
tRCD
tCSH
tRSH
tROH
tcR
ta(RAS)
ta(CA)
ta(CAS)
ta(G)
tw(RASL)
tw(CASL)
tsu(R-CAS)
th(RAS-R)
th(CAS-R)
th(RAS-CA)
th(RASH-CA)
tRASL-CASL
tRASL-CASH
tCASL-RASH
tGL-RASH
130
70
20
0
0
0
70
5
20
70
20
10
150
ns
70
80 ns
35
40 ns
20
20 ns
20
20 ns
80 10000 10000 ns
20 10000 10000 ns
0
ns
0
ns
0
ns
80
ns
5
ns
20
50
60 ns
80
ns
20
ns
10
ns
Remarks: see page 7
December 12, 1997
5
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