MT91L62 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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MT91L62 Datasheet PDF : 19 Pages
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MT91L62
Data Sheet
Pin Description (continued)
Pin #
19
20
Name
Ain-
Ain+
Description
Inverting Analog Input. No external anti-aliasing is required.
Non-Inverting Analog Input. Non-inverting input. No external anti-aliasing is required.
Overview
The 3 V Single-Rail Codec features complete Analog/Digital and Digital/Analog conversion of audio signals
(Filter/Codec) and an analog interface to a standard analog transmitter and receiver (analog Interface). The
receiver amplifier is capable of driving a 20 k ohm load.
Functional Description
Filter/Codec
The Filter/Codec block implements conversion of the analog 0-3.3 kHz speech signals to/from the digital domain
compatible with 64 kb/s PCM B-Channels. Selection of companding curves and digital code assignment are
programmable. These are ITU-T G.711 A-law or µ-Law, with true-sign/Alternate Digit Inversion.
The Filter/Codec block also implements a transmit audio path gain in the analog domain. Figure 3 depicts the
nominal half-channel for the MT91L62.
The internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide
dynamic range from a single 3 volt supply design. This fully differential architecture is continued into the Analog
Interface section to provide full chip realization of these capabilities for the external functions.
A reference voltage (VRef), for the conversion requirements of the Codec section, and a bias voltage (VBias), for
biasing the internal analog sections, are both generated on-chip. VBias is also brought to an external pin so that it
may be used for biasing external gain setting amplifiers. A 0.1 µF capacitor must be connected from VBias to analog
ground at all times. Likewise, although VRef may only be used internally, a 0.1 µF capacitor from the VRef pin to
ground is required at all times. The analog ground reference point for these two capacitors must be physically the
same point. To facilitate this the VRef and VBias pins are situated on adjacent pins.
The transmit filter is designed to meet ITU-T G.714 specifications. An anti-aliasing filter is included. This is a
second order lowpass implementation with a corner frequency at 25 kHz.
The receive filter is designed to meet ITU-T G.714 specifications. Filter response is peaked to compensate for the
sinx/x attenuation caused by the 8 kHz sampling rate.
Companding law selection for the Filter/Codec is provided by the A/µ companding control pin. Table 1
illustrates these choices.
Code
+ Full Scale
+ Zero
-Zero
(quiet code)
- Full Scale
ITU-T (G.711)
µ-Law
A-Law
1000 0000
1010 1010
1111 1111
1101 0101
0111 1111
0101 0101
0000 0000
0010 1010
Table 1 - Law Selection
3
Zarlink Semiconductor Inc.
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