MT93L16 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT93L16

Low-Voltage Acoustic Echo Canceller

Zarlink Semiconductor Inc 

Preliminary Information

MT93L16

FUNCTIONAL DESCRIPTION FOR USING THE BOOTABLE RAM

BOOTLOAD MODE - Microport Access is to bootload RAM (BRAM)

R/W

Address

Data

BRC Register

W

Bits

C3C2C1C0

W

X100

R

R

3fh

(= 1 1 1 1 1 1 b)

other than 3fh

1x xxxxb

0x xxxxb

Writes "data" to BRC reg.

- Bootload frozen; BRAM contents are NOT affected.

Writes "data" to next byte in BRAM (bootloading.)

Reads back "data" = BRC reg value.

- Bootload frozen; BRAM contents are NOT affected.

Reads back "data" = SIG reg value.

- Bootload frozen; BRAM contents are NOT affected.

NON-BOOTLOAD MODE - Microport Access is to device registers (DREGs)

BRC Register

R/W

Bits

C3C2C1C0

W

X000

R

Address

Data

any

(= a5 a4 a3 a2 a1 a0 b)

Writes "data" to corresponding DREG.

any

(= a5 a4 a3 a2 a1 a0 b)

Reads back "data" = corresponding DREG value.

PROGRAM EXECUTION MODES

C3C2C1C0

0000

C3C2C1C0

0100

Execute program in ROM, bootload mode disabled.

- BRAM address counter reset to initial (ready) state.

- SIG reg reseeded to initial (ready) state

Execute program in ROM, while bootloading the RAM.

- BRAM address counter increments on microport writes (except to 3fh)

- SIG reg recalculates signature on microport writes (except to 3fh)

C3C2C1C0

1000

Execute program in RAM, bootload mode disabled.

- BRAM address counter reset to initial (ready) state.

- SIG reg reseeded to initial (ready) state

C3C2C1C0

1100

- NOT RECOMMENDED -

(Execute program in RAM, while bootloading the RAM)

Table 5 - Bootload RAM Control (BRC) Register States

Note: bits C1 C0 are reserved, and must be set to zero.

Resetting the bootload bit (C2) in the BRC register to

0 (see Register Summary) exits bootload mode,

resetting the signature (SIG) register and internal

address generator for the next bootload. A hardware

reset (RESET=0) similarly returns the MT93L16 to

the ready state for the start of a bootload.

Once the program has been loaded, to begin

execution from RAM, bootload mode must be

disabled (BOOT bit, C2=0) and execution from RAM

enabled (RAM_ROMb bit, C3=1) by setting the

appropriate bits in the BRC register. During the

bootload process, however, ROM program execution

(RAM_ROMb bit, C3=0) should be selected. See

Table 5 for the effect of the BRC register settings on

Microport accesses and on program execution.

Following program loading and enabling of execution

from RAM, it is recommended that users set the

software reset bit in the Main Control (MC) register,

to ensure that the device updates the default register

values to those of the new program in RAM. Note: it

is important to use a software reset rather than a

hardware (RESET=0) reset, as the latter will return

the device to its default settings (which includes

execution from program ROM instead of RAM.)

To verify which code revision is currently running,

users can access the Firmware Revision Code

(FRC) register (see Register Summary). This

register reflects the identity code (revision number)

of the last program to run register initialization (which

follows a software or hardware reset.)

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