MT90823AP1 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT90823AP1

3 V Large Digital Switch

Zarlink Semiconductor Inc 

MT90823

Data Sheet

Pin Description (continued)

Pin #

84 100 100

PLCC MQFP LQFP

120

BGA

Name

Description

76

57

54

B11

ODE Output Drive Enable (5 V Tolerant Input): This is the

output enable control for the STo0-15 serial outputs.

When ODE input is low and the OSB bit of the IMS

register is low, STo0-15 are in a high impedance state.

If this input is high, the STo0-15 output drivers are

enabled. However, each channel may still be put into a

high impedance state by using the per channel control

bit in the connection memory.

77 - 58-65 55 - A11,B10,A10,B9, STo0 - 7 Data Stream Output 0 to 7 (5 V Tolerant Three-state

84

62

A9,A8,B8,A7

Outputs): Serial data Output stream. These streams

have selectable data rates of 2.048, 4.096 or

8.192 Mb/s.

- 1 - 4, 1 - 2,

27 - 24 -

30, 27,

51 - 49 -

54

52,

77 - 74 -

80

77,

99 -

100

NC No connection.

Device Overview

The MT90823 Large Digital Switch is capable of switching up to 2,048 × 2,048 channels. The MT90823 is designed

to switch 64 kb/s PCM or N x 64 kb/s data. The device maintains frame integrity in data applications and minimum

throughput delay for voice applications on a per channel basis.

The serial input streams of the MT90823 can have a bit rate of 2.048, 4.096 or 8.192 Mbit/s and are arranged in

125 µs wide frames, which contain 32, 64 or 128 channels, respectively. The data rates on input and output

streams are identical.

By using Zarllink’s message mode capability, the microprocessor can access input and output time-slots on a per

channel basis. This feature is useful for transferring control and status information for external circuits or other ST-

BUS devices. The MT90823 automatically identifies the polarity of the frame synchronization input signal and

configures its serial streams to be compatible to either ST-BUS or GCI formats.

Two different microprocessor bus interfaces can be selected through the Input Mode pin (IM): Non-multiplexed or

Multiplexed. These interfaces provide compatibility with multiplexed and Motorola multiplexed/non-multiplexed

buses.

The frame offset calibration function allows users to measure the frame offset delay using a frame evaluation pin

(FE). The input offset delay can be programmed for individual streams using internal frame input offset registers,

see Table 11.

The internal loopback allows the ST-BUS output data to be looped around to the ST-BUS inputs for diagnostic

purposes.

8

Zarlink Semiconductor Inc.

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