MT9160B 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT9160B

ISO²-CMOS 5 Volt Multi-Featured Codec (MFC) Advance Information

Zarlink Semiconductor Inc 

MT9160B/61B

Advance Information

Motorola/National operation. Refer to the relative

timing diagrams of Figures 5 and 6.

Receive data is sampled on the rising edge of SCLK

while transmit data is made available concurrent with

the falling edge of SCLK.

Flexible Digital Interface

A serial link is required to transport data between the

MT9160B/61B and an external digital transmission

device. The MT9160B/61B utilizes the ST-BUS

architecture defined by Zarlink Semiconductor but

COMMAND/ADDRESS ➄ ➀

DATA INPUT/OUTPUT

➀

➃ COMMAND/ADDRESS:

DATA 1

RECEIVE

D0

D1

D2

D3

D4

D5

D6

D7

D0 D1 D2 D3 D4 D5 D6 D7

D0 D1 D2 D3 D4 D5 D6 D7

DATA 1

TRANSMIT

SCLK y

D0 D1 D2 D3 D4 D5 D6 D7

D0 D1 D2 D3 D4 D5 D6 D7

CS

➃

➂

➂

➀ Delays due to internal processor timing which are transparent.

y The MT9160:-latches received data on the rising edge of SCLK.

-outputs transmit data on the falling edge of SCLK.

➂ The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The

subsequent byte is always data until terminated via CS returning high.

➃ A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.

➄ The COMMAND/ADDRESS byte contains: 1 bit - Read/Write

3 bits - Addressing Data

4 bits - Unused

D7

D0

X

X

X

X A2 A1 A0 R/W

Figure 4 - Serial Port Relative Timing for Intel Mode 0

COMMAND/ADDRESS ➄ ➀

DATA INPUT/OUTPUT

➀

➃ COMMAND/ADDRESS:

DATA 2

RECEIVE

D7

D6

D5

D4

D3

D2

D1

D0

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

DATA 1

TRANSMIT

SCLK y

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

CS

➃

➂

➂

➀ Delays due to internal processor timing which are transparent.

y The MT9160:-latches received data on the rising edge of SCLK.

-outputs transmit data on the falling edge of SCLK.

➂ The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The

subsequent byte is always data until terminated via CS returning high.

➃ A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.

➄ The COMMAND/ADDRESS byte contains: 1 bit - Read/Write

3 bits - Addressing Data

4 bits - Unused

D7

R/W X X

D0

X A2 A1 A0 X

Figure 5 - Serial Port Relative Timing for Motorola Mode 00/National Microwire

84

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