MT9300 데이터 시트보기 (PDF) - Mitel Networks
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MT9300 Datasheet PDF : 29 Pages
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Advance Information
Registers Description
Echo Canceller A, Control Register A1
MT9300
Read/Write Address: 00H + Base Address
7654321
Reset INJDis BBM PAD Bypass AdpDis 0
0
ExtDl
Echo Canceller B, Control Register B1
76543210
Reset INJDis BBM PAD Bypass AdpDis 1
0
Reset Value:
00H.
Read/Write Address: 20H + Base Address
Reset Value:
02H.
Bit
Name
Description
7
Reset
When high, the power-up initialization is executed which presets all register bits
including this bit and clears the Adaptive Filter coefficients.
6
INJDis
When high, the noise injection process is disabled. When low noise injection is
enabled.
5
BBM
When high the Back to Back configuration is enabled.
When low the Normal configuration is enabled.
Note: Do not enable Extended-Delay and BBM configurations at the same time.
Always set both BBM bits of the two echo cancellers (Control Register A1 and Control
Register B1) of the same group to the same logic value to avoid conflict.
4
PAD
When high, 12dB of attenuation is inserted into the Rin to Rout path.
When low the Rin to Rout path gain is 0dB.
3
Bypass When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The
Adaptive Filter coefficients are set to zero and the filter adaptation is stopped.
When low, output data on both Sout and Rout is a function of the echo canceller
algorithm.
2
AdpDis When high, echo canceller adaptation is disabled. The MT9300 cancels echo.
When low, the echo canceller dynamically adapts to the echo path characteristics.
1
0 or 1
Bits marked as “1” or “0” are reserved bits and should be written as indicated.
0
ExtDl
When high, Echo Cancellers A and B of the same group are internally cascaded into
or
one 128ms echo canceller.
0
When low, Echo Cancellers A and B of the same group operate independently.
Note: Do not enable both Extended-Delay and BBM configurations at the same time.
Control Register B1 bit-0 is a reserved bit and should be written “0”.
13
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