MT9126 데이터 시트보기 (PDF) - Mitel Networks
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MT9126 Datasheet PDF : 22 Pages
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Preliminary Information
MT9126
BCLK
ENB1
ENB2/F0od
PCMi/o1
PCMi/o2
ADPCM i/o
32 kb/s
24 kb/s
B1
B2
7654321076543210
B3
B4
7654321076543210
12341234 12341234
B1
B2
B3
B4
123x123x 123x123x
ADPCM i/o
B1 B2 B3 B4 B1 B2 B3 B4
16 kb/s
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel strobe boundaries
Two frame delay from data input to data output
1 21 2 1 2 1 21 2 1 2 1 2 1 2
SEL = 0
SEL = 1
SEL for 16 kb/s only
Figure 4 - SSI 8-Bit Companded PCM Relative Timing
BCLK
EN1
ENB1
... (2.048 MHz only)
Notes: S = 3 bits sign extension
µ−Law is 13 bit 2’s complement data (bits 0 -12)
A-Law is 12 bit 2’s complement data (shifted left once and utilizing
bits 1 - 12, bit 0 not defined)
ENB2/F0od
PCMi/o1
PCMi/o2
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0 SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
B1
B2
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0 SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
B3
B4
32 kb/s
ADPCM i/o
24 kb/s
1234 1234 1234 1234
B1 B2 B3 B4
123x 123x 123x 123x
1234 1234
B3 B4
123x 123x
12 12 12 12 12 12 12 12
BBBBBBBB
ADPCMi/o
16 kb/s
12341234
SEL = 0 AAAAAAAAAASEL = 1
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel strobe boundaries
Two frame delay from data input to data output
12 12 12 12
BBBB
1234
SEL = 1
Figure 5 - SSI 16-Bit Linear PCM Relative Timing
SEL for 16 kb/s only
8-41
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