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MT9126AE

Quad ADPCM Transcoder

Mitel Networks 

MT9126

Preliminary Information

from ADPCMi are expanded into four 16-bit uniform

PCM dual-octets on PCMo1 and PCMo2. 16-bit

uniform PCM are received and transmitted most

significant bit first starting with b15 and ending with

b0. ADPCM data are transferred most significant bit

first starting with I1 and ending with I4 for 32 kbit/s

and ending with I3 for 24 kbit/s operation (i.e., I4 is

don’t care).(See Figures 5 & 8.)

16 kbit/sADPCM mode

When SEL is set to 0, the four, 2-bit ADPCM words

are transmitted/received on ADPCMo/i during the

ENB1 time-slot in SSI mode and during the B1

timeslot in ST-BUS mode. When SEL is set to 1, the

four, 2-bit ADPCM words are transmitted/received

on ADPCMo/i during the ENB2 timeslot in SSI mode

and during the B2 timeslot in ST-BUS mode. (See

Figures 5 & 8.)

PCM Law Control (A/µ, FORMAT)

The PCM companding/coding law invoked by the

transcoder is controlled via the A/µ and FORMAT

pins. ITU-T G.711 companding curves, µ-Law and

A-Law, are selected by the A/µ pin (0=µ-Law;

1=A-Law). Per sample, digital code assignment can

conform to ITU-T G.711 (when FORMAT=1) or to

Sign-Magnitude coding (when FORMAT=0). Table 1

illustrates these choices.

FORMAT

0

1

Sign-

ITU-T (G.711)

PCM Code Magnitude

A/µ = 0 or 1 (A/µ = 0) (A/µ = 1)

+ Full Scale 1111 1111 1000 0000 1010 1010

+ Zero

1000 0000 1111 1111 1101 0101

- Zero

0000 0000 0111 1111 0101 0101

- Full Scale 0111 1111 0000 0000 0010 1010

Table 1 - Companded PCM

Power Down

Setting the PWRDN pin low will asynchronously

cause all internal operation to halt and the device to

go to a power down condition where no internal

clocks are running. Output pins C2o, EN1, EN2,

PCMo1, PCMo2 and ADPCMo and I/O pin F0od/

ENB2 are forced to a high-impedance state.

Following the reset (i.e., PWRDN pin brought high)

8-40

and assuming that clocks are applied to the MCLK

and BCLK pins, the internal clocks will still not begin

to operate until the first frame alignment is detected

on the ENB1 pin for SSI mode or on the F0i pin for

ST-BUS mode. The C2o clock and EN1, EN2 pins

will not start operation until a valid frame pulse is

applied to the F0i pin. If the F0i pin remains low for

longer than 2 cycles of MCLK then the C2o pin will

top toggling and will stay low. If the F0i pin is held

high then the C2o pin will continue to operate. In ST-

BUS mode the EN1 and EN2 pins will stop toggling if

the frame pulse (F0i) is not applied every frame.

Master Clock (MCLK)

A minimum 4096 kHz master clock is required for

execution of the transcoding algorithm. The

algorithm requires 512 cycles of MCLK during one

frame for proper operation. For SSI operation this

input, at the MCLK pin, may be asynchronous with

the 8 kHz frame provided that the lowest frequency

and deviation due to clock jitter still meets the strobe

period requirement of a minimum of 512 tC4P -

25%tC4P (see Figure 3). For example, a system

producing large jitter values can be accommodated

by running an over-speed MCLK that will ensure a

minimum 512 MCLK cycles per frame is obtained.

The minimum MCLK period is 61 nSec, which

translates to a maximum frequency of 16.384 MHz.

Extra MCLK cycles (>512/frame) are acceptable

since the transcoder is aligned by the appropriate

strobe signals each frame.

ENB1

MCLK

512 tC4P - 25%tC4P Minimum

Figure 3 - MCLK Minimum Requirement

Bit Clock (BCLK)

For SSI operation the bit rate, for both ADPCM and

PCM ports, is determined by the clock input at BCLK.

BCLK must be eight periods in duration and

synchronous with the 8 kHz frame inputs at ENB1

and ENB2. Data is sampled at PCMi1/2 and at

ADPCMi concurrent with the falling edge of BCLK.

Data is available at PCMo1/2 and ADPCMo

concurrent with the rising edge of BCLK. BCLK may

be any rate between 128 kHz and 4096 kHz. For ST-

BUS operation BCLK is ignored (tie to VSS) and the

bit rate is internally set to 2048 kbit/s.

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