MT90401 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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MT90401 Datasheet PDF : 38 Pages
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MT90401
Data Sheet
Pin Description (continued)
Pin # Name
Description
62
OE Output Enable (Input). Tie high for normal operation. Tie low to force output clocks pins
F16, F8, C16, C8, C4, C2 to a high impedance state.
63
CS Chip Select (5 V tolerant Input). This active low input enables the non-multiplexed
Motorola parallel microprocessor interface of the MT90401. When CS is set to high, the
microprocessor interface is idle and all bus I/O pins will be in a high impedance state.
64
RST RESET (5 V tolerant Input). This active low input puts the MT90401 in a reset condition.
RST should be set to high for normal operation. The MT90401 should be reset after power-
up and after the selected reference frequency is changed. The RST pin must be held low for
a minimum of 1msec. to reset the device properly.
65
HW Hardware Mode (Input). If this pin is tied low, the device is in microport mode and is
controlled via the microport. If it is tied high, the device is in hardware mode and is
controlled via the control pins MS1, MS2, FS1, FS2, FLOCK and SONET/SDH.
66-69 D0 - D3 Data 0 to Data 3 (5 V tolerant Three-state I/O). These signals combined with D4-D7 form
the bidirectional data bus of the parallel processor interface (D0 is the least significant bit).
70
VSS8 Digital ground. 0 Volts.
71
IC
Internal Connection. Tie low for normal operation.
72
IC
Internal Connection. Tie low for normal operation.
73
74-77
VDD5
D4 - D7
Positive Power Supply. Digital supply.
Data 4 to Data 7 (5 V tolerant Three-state I/O). These signals combined with D0-D3 form
the bidirectional data bus of the parallel processor interface (D7 is the most significant bit).
78
R/W Read/Write Select (5 V tolerant Input). This input controls the direction of the data bus
D[0:7] during a microprocessor access. When R/W is high, the parallel processor is reading
data from the MT90401. When low, the parallel processor is writing data to the MT90401.
79
A0
Address 0 (5 V tolerant Input). Address input for the parallel processor interface. A0 is the
least significant input.
80
IC
Internal Connection. Tie low for normal operation.
6
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