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MT8986APR1

CMOS ST-BUS™ FAMILY Multiple Rate Digital Switch

Zarlink Semiconductor Inc 

MT8986

Data Sheet

Pin Description (continued)

Pin #

40 44 44

DIP PLCC QFP

Name

Description

19 22 16 DS/RD Data Strobe/Read (Input). When non-multiplexed CPU bus or Motorola

multiplexed bus (44 pin only) are selected, this input is DS. This active high input

works in conjunction with CS to enable read and write operation.

For Intel/National multiplexed bus (44 pin only), this input is RD. This active low

input configures the data bus lines (AD0-AD7) as outputs.

20 23 17 R/W\WR Read/Write \ Write (Input). In case of non-multiplexed and Motorola multiplexed

buses (44 pin only), this input is R/W. This input controls the direction of the data

bus lines (AD0-AD7) during a microprocessor access.

With Intel/National multiplexed timing (44 pin only), this input is WR. This active

low signal configures the data bus lines (AD0-AD7) as inputs.

21 24 18

CS Chip Select (Input). Active low input enabling a microprocessor read or write of

the control register or internal memories.

22-29 25-27 19-21

29-33 23-27

AD7-

AD0

Data Bus (Bidirectional): These pins provide microprocessor access to the

internal control registers, connection memories high and low and data memories.

In multiplexed bus mode (44 pin) these pins also provide the input address to the

internal Address Latch circuit.

30 34 28

VSS Ground.

31 35 29 STo7/A7 ST-BUS Output 7/Address 7 input (Three-state output/input). The function of

this pin is determined by the switching configuration enabled. If non-multiplexed

CPU bus is used along with data rates employing 8.192 Mb/s rates, this pin

provides A7 address input function. For 2.048 Mb/s applications or when

multiplexed CPU bus (44 pin only) is selected, this pin assumes STo7 function.

See Tables 1, 2, 6 & 7 for more details.

Note that for applications where A7 input and STo7 output are required

simultaneously (e.g., 8.192 to 2.048 Mb/s rate conversion), the A7 input should

be connected to pin STi7/A7.

32 36 30 STo6/A6 ST-BUS Output 6/Address 6 input (Three-state output/input). The function of

this pin is determined by the switching configuration enabled. If non-multiplexed

CPU bus is used along with a higher data rate employing 8.192 or 4.096 Mb/s,

this pin provides the A6 address input function. For 2.048 Mb/s applications or

when multiplexed CPU bus (44 pin only) is selected, this pin assumes STo6

function. See Tables 1, 2, 6 & 7 for more details.

Note that for applications where both A6 input and STo6 output are required

simultaneously (e.g., 4.096 to 2.048 Mb/s or 8.192 to 2.048 Mb/s rate conversion

applications), the A6 input should be connected to pin STi6/A6.

33-38 37-39 31-33 STo5-0 ST-BUS Outputs 5 to 0 (Three-state Outputs). Serial data output streams.

41-43 35-37

These serial streams may be composed of 32, 64 and 128 channels at data rates

of 2.048, 4.096 or 8.192 Mbit/s, respectively.

39 44 38 ODE Output Drive Enable (Input). This is the output enable input for the STo0 to

STo9 serial outputs. If this input is low STo0-9 are high impedance. If this input

is high each channel may still be put into high impedance by using per-channel

control bits in Connect Memory High.

4

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