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MT8979AP

ISO-CMOS ST-BUS™ FAMILY CEPT PCM 30/CRC-4 Framer & Interface

Zarlink Semiconductor Inc 

MT8979

Data Sheet

Synchronization is included within the CEPT bit stream in the form of a bit pattern inserted into timeslot 0. The

contents of timeslot 0 alternate between the frame alignment pattern and the non-frame alignment pattern as

described in Figure 4. Bit 1 of the frame alignment and non-frame alignment bytes have provisions for additional

protection against false synchronization or enhanced error monitoring. This is described in more detail in the

following section.

In order to accomplish multiframe synchronization, a 16 frame multiframe is defined by sending four zeros in the

high order quartet of timeslot 16 frame 0, i.e., once every 16 frames (see Figure 5). The CEPT format has four

signalling bits, A, B, C and D. Signalling bits for all 30 information channels are transmitted in timeslot 16 of frames

1 to 15. These timeslots are subdivided into two quartets (see Table 6).

Bit Number

Timeslot 0 containing the

frame alignment signal

Timeslot 0 containing the non-

frame alignment signal

1

Reserved for

International

use (1)

Reserved for

International

use (2)

2

3

0

0

4

5

6

7

8

1

1

0

1

1

1 Alarm indication to the See See See See See

remote PCM multiplex Note Note Note Note Note

equipment

#3

#3

#3

#3

#3

Figure 4 - Allocation of Bits in Timeslot 0 of the CEPT Link

Note 1 : With CRC active, this bit is ignored.

Note 2 : With SiMUX active, this bit transmits SMF CRC results in frames 13 and 15

Note 3 : Reserved for National use

.

Timeslot 16 of frame 0

Timeslot 16 of frame 1

Timeslot 16 of frame 15

0000

XYXX

ABCD bits for

telephone

channel 1

(timeslot 1)

ABCD bits for

telephone

channel 16

(timeslot 17)

•••

ABCD bits for

telephone

channel 15

(timeslot 15)

ABCD bits for

telephone

channel 30

(timeslot 31)

Figure 5 - Allocation of Bits in Timeslot 16 of the CEPT Link

Cyclic Redundancy Check (CRC)

An optional cyclic redundancy check (CRC) has been incorporated within CEPT bit stream to provide additional

protection against simulation of the frame alignment signal, and/or where there is a need for an enhanced error

monitoring capability. The CRC process treats the binary string of ones and zeros contained in a submultiframe

(with CRC bits set to binary zero) as a single long binary number. This string of data is first multiplied by x4 then

divided by the generating polynomial x4+x+1. This division process takes place at both the transmitter and receiver

end of the link. The remainder calculated at the receiver is compared to the one received with the data over the

link. If they are the same, it is of high probability that the previous submultiframe was received error free.

The CRC procedure is based on a 16 frame multiframe, which is divided into two 8 frame submultiframes (SMF).

The frames which contain the frame alignment pattern contain the CRC bits, C1 to C4 respectively, in the bit 1

position. The frames which contain the non-frame alignment pattern contain within the bit 1 position, a 6 bit CRC

multiframe alignment signal and two spare bits (in frames 13 and 15), which are used for CRC error performance

reporting (refer to Figure 6). During the CRC encoding procedure the CRC bit positions are initially set at zero. The

remainder of the calculation is stored and inserted into the respective CRC bits of the next SMF. The decoding

process repeats the multiplication division process and compares the remainder with the CRC bits received in the

next SMF.

5

Zarlink Semiconductor Inc.

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