MT9075B 데이터 시트보기 (PDF) - Mitel Networks

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MT9075B

E1 Single Chip Transceiver

Mitel Networks 

Preliminary Information

MT9075B

used to control the transmit channel associated

signalling. The DSTi and DSTo streams contain the

transmit and receive voice and digital data.

Identification Code

The MT9075B shall be identified by the code

10101010, read from the identification code status

register (page 03H, address 1FH).

Reset Operation (Initialization)

The MT9075B can be reset using the hardware

RESET pin (pin 11 in PLCC, pin 84 in MQFP, see pin

description for external reset circuit requirements) or

the software reset bit RST (page 01H, address 11H).

When the device emerges from its reset state it will

begin to function with the default settings described

in Table 6. A reset operation takes 1 full frame (125

us) to complete.

Function

Status

Mode

Loopbacks

Transmit FAS

Transmit non-FAS

Transmit MFAS (CAS)

Data Link

CRC Interworking

Signalling

ABCD Bit Debounce

Interrupts

RxMF Output

Error Insertion

HDLCs

Counters

Tx Message Buffer

Per Time Slot Control

Buffer

Termination

Deactivated

Cn0011011

1/Sn1111111

00001111

Deactivated

Activated

CAS Registers

Deactivated

Interrupt Mask Word

Zero unmasked, all

others masked;

interrupts not suspended

Signalling Multiframe

Deactivated

Deactivated

Cleared

All locations set to 54H

All locations cleared

Table 6 - Reset Status

Transmit AIS Operation

The pin TAIS (Transmit AIS, pin 60 in PLCC, pin 48 in

MQFP) allows an all ones signal to be transmitted

from the point of power-up without the need to write

any control registers. During this time the IRQ pin is

tristated. After the interface has been initialized

normal operation can take place by making TAIS

high.

National Bit Buffers

Table 7 shows the contents of the transmit and

receive Frame Alignment Signals (FAS) and Non-

frame Alignment Signals (NFAS) of time slot zero of

a PCM 30 signal. Even numbered frames (CRC

Frame # 0, 2, 4,...) are FASs and odd numbered

frames (CRC Frame # 1, 3, 5,...) are NFASs. The bits

of each channel are numbered 1 to 8, with bit 1 being

the most significant and bit 8 the least significant.

CRC

PCM 30 Channel Zero

CRC Frame/

Type 1 2 3 4 5 6 7 8

0/FAS

1/NFAS

C1 0

01

2/FAS

3/NFAS

C2 0

01

4/FAS

5/NFAS

C3 0

11

6/FAS

7/NFAS

C4 0

01

8/FAS

9/NFAS

C1 0

11

10/FAS C2 0

11/NFAS 1 1

12/FAS C3 0

13/NFAS E1 1

14/FAS C4 0

15/NFAS E2 1

011011

A Sa4 Sa5 Sa6 Sa7 Sa8

011011

A Sa4 Sa5 Sa6 Sa7 Sa8

011011

A Sa4 Sa5 Sa6 Sa7 Sa8

011011

A Sa4 Sa5 Sa6 Sa7 Sa8

011011

A Sa4 Sa5 Sa6 Sa7 Sa8

011011

A Sa4 Sa5 Sa6 Sa7 Sa8

011011

A Sa4 Sa5 Sa6 Sa7 Sa8

011011

A Sa4 Sa5 Sa6 Sa7 Sa8

Table 7 - FAS and NFAS Structure

indicates position of CRC-4 multiframe alignment signa

Table 8 illustrates the organization of the MT9075B

transmit and receive national bit buffers. Each row is

an addressable byte of the MT9075B national bit

buffer, and each column contains the national bits of

an odd numbered frame of each CRC-4 Multiframe.

The transmit and receive national bit buffers are

located at page 0DH and 0EH respectively.

15

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