HN58S65A 데이터 시트보기 (PDF) - Hitachi -> Renesas Electronics

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HN58S65A

64 k EEPROM (8-kword × 8-bit) Ready/Busy function

Hitachi -> Renesas Electronics 

HN58S65A Series

Write Cycle

Parameter

Symbol Min*2 Typ

Test

Max

Unit conditions

Address setup time

t AS

0

—

—

ns

Address hold time

t AH

150

—

—

ns

CE to write setup time (WE controlled) tCS

0

—

—

ns

CE hold time (WE controlled)

t CH

0

—

—

ns

WE to write setup time (CE controlled) tWS

0

—

—

ns

WE hold time (CE controlled)

t WH

0

—

—

ns

OE to write setup time

t OES

0

—

—

ns

OE hold time

t OEH

0

—

—

ns

Data setup time

t DS

150

—

—

ns

Data hold time

t DH

0

—

—

ns

WE pulse width (WE controlled)

t WP

200

—

—

ns

CE pulse width (CE controlled)

t CW

200

—

—

ns

Data latch time

t DL

200

—

—

ns

Byte load cycle

t BLC

0.4

—

30

µs

Byte load window

t BL

100

—

—

µs

Write cycle time

t WC

—

—

15*3

ms

Time to device busy

t DB

120

—

—

ns

Write start time

t DW

0*4

—

—

ns

Notes: 1. tDF is defined as the time at which the outputs achieve the open circuit conditions and are no

longer driven.

2. Use this device in longer cycle than this value.

3. tWC must be longer than this value unless polling techniques or RDY/Busy are used. This

device automatically completes the internal write operation within this value.

4. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy are

used.

5. A6 through A12 are page addresses and these addresses are latched at the first falling edge

of WE.

6. A6 through A12 are page addresses and these addresses are latched at the first falling edge

of CE.

7. See AC read characteristics.

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