MSM7660 데이터 시트보기 (PDF) - Oki Electric Industry
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MSM7660 Datasheet PDF : 35 Pages
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¡ Semiconductor
MSM7660
Pin
43 to 50
51
52
53 to 60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Symbol
Y[7 to 0]
GND
VDD5
C[7 to 0]
GND
VDD3
TEST0
TEST1
ODD
VVALID
HVALID
VSYNC_L
HSYNC_L
CSYNC_L
HSY
HCL
HDET
VDD5
VDD3
GND
CLKDIV
CLKO
CLKX2O
CLKX2
I/O
Description
O Luminance signal output pin
Peripheral I/O power supply (5.0 V typ.)
O Chrominance signal output pin
Internal logic power supply (3.3 V typ.)
I Input pin for testing. Normally use this pin at open state or "H" level.
I Input pin for testing. Normally use this pin at open state or "H" level.
O Field display output pin
Outputs "H" for odd field.
O Vertical valid line timing output pin
O Horizontal valid pixel timing output pin
O V sync output pin
O H sync output pin
O Composite sync output pin
O Sync chip timing output pin for AD converter
O Clamp timing output pin for AD converter
O HLOCK synchronization detection display output pin (Outputs "H" when H
synchronization is established.)
Peripheral I/O power supply (5.0 V typ.)
Internal logic power supply (3.3 V typ.)
I Clock select input pin
Inputs "H" when a half CLKX2 is used as the internal clock.
O Clock output pin
Outputs internal clock.
O Clock output pin
Bypasses clock input and outputs clock input.
I Clock input pin (a clock one or two times the sampling clock is input)
[Clock supply method and handling]
1.Supplying double pixel clock from external 2.Supplying pixel clock from external supply
supply source
source
CLKDIV
CLKDIV
Clock supply source
CLKX2
X
XL
Clock supply source
CLKX2
X
XL
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