MSM7650 데이터 시트보기 (PDF) - Oki Electric Industry
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MSM7650 Datasheet PDF : 34 Pages
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¡ Semiconductor
MSM7650
PIN DESCRIPTIONS (2/2)
Pin
46
47
48
49
50
51
52
53
54
55 to 57
58
59
60
61
62
63
64
65 to 72
73 to 80
I/O Symbol
Description
I
TEST4 Input pin 4 for testing. Normally, fixed to "0".
O
TOUT1 Output pin for testing
O
TOUT2 Output pin for testing
I
ADRS I2C-bus subaddress setting pin. One of two addresses switchable can be
selected as subaddress.
1: 1000110/0: 1000100
I/O
SDA
I2C-bus data pin
I
SCL
I2C-bus clock pin
I
RESET_L System reset pin. "1" at an open state by an internal pull-up resistor
I
MS
Operation mode select signal pin for synchronization circuit.
1: master/0: slave. "1" at an open state by an internal pull-up resistor
I INTERLACE Interlace/noninterlace select signal pin.
1: interlaced/0: noninterlaced. "1" at an open state by an internal pull-up
resistor
I
MODE[2] Video mode select pins
to MODE[0] These pins are valid when MR[7] is "1".
000: NTSC CCIR 001: NTSC Square Pixel 010: NTSC 4Fsc
100: PAL CCIR 101: PAL Square Pixel
"000" at an open state by an internal pull-down resistor
I
OLC
Transparent control signal
Overlay signal is displayed when this pin is "H".
I
OLB
Overlay text color (Blue component)
I
OLG
Overlay text color (Green component)
I
OLR
Overlay text color (Red component)
GND Digital GND
I
VDD3
3.3V power supply
VDD5
5.0V power supply
I YD0 to YD7 Digital image luminance signal data input pin
Level is based on ITU-601. YD7 is MSB.
CD0 to CD7 Digital image chrominance signal data input pin
Level is based on ITU-601. CD7 is MSB.
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