MSM7582 데이터 시트보기 (PDF) - Oki Electric Industry
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MSM7582 Datasheet PDF : 24 Pages
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¡ Semiconductor
MSM7582/7582B
ENV
Quadrature modulation signal envelope ( I2 + Q2 )output.
Its output level is 500 mVPP with 1.6 Vdc as a center value. The output pin load conditions are
: R ≥ 10 kW, C ≤ 20 pF. The gain of this output can be adjusted using the control register CR2 – B7
to B4.
This pin is also used to monitor eye pattern, AFC Compensating signal, and phase defection of
the demodulator block during the test mode. Refer to the description of the control register for
details.
SG
Internal reference voltage output.
The output voltage is about 2.0 V. A bypass capacitor should be connected between this pin and
the AGND pin.
PDN0, PDN1, PDN2
Inputs for power-down control.
PDN0 controls the standby / communication modes, PDN1 controls the modulator, and PDN2
controls the demodulator. Refer to Table 1 for details.
Table-1 Power Down Control
Standby
Mode
Communication
Mode
PDN0 PDN2 PDN1
Function
0 0/1 1 All power-down. The control register is reset.
0
0
0 All power-down. The control register is not reset.
Modulator power is off (VREF and PLL power are also off).
0
1
0
Demodulator power is on.
Modulator power is off (VREF and PLL power is on).
1
0
0 I and Q outputs are in a high-impedance state.
Only demodulator clock recovery block power is on.
Modulator power is on
1
0
1
Only demodulator clock recovery block power is on.
Modulator power is off (VREF and PLL power is on).
1
1
0 I and Q outputs are in a high-impedance state.
Demodulator power is on.
Modulator power is on
1
1
1
Demodulator power is on.
Mode
Mode A
Mode B
Mode C
Mode D
Mode E
Mode F
Mode G
VDD
+3 V power supply voltage.
AGND
Analog signal ground.
DGND
Digital signal ground.
AGND and DGND are not connected in the device. This pin should be tied to the AGND pin on
the PCB as close as possible from the device.
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