MSM7581 데이터 시트보기 (PDF) - Oki Electric Industry
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MSM7581 Datasheet PDF : 18 Pages
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¡ Semiconductor
MSM7581
RES1, RES2, RES3, RES4
Algorithm reset signal input pins for each Channel (1 - 4) .
When digital “0” is applied, the entire transcoder goes to the initial state.
This reset is defined by ITU-T G.721 and is an optional reset.
The reset width (during "L") should be 125 ms or more.
BCKA1 - 4
Bit clock input pins used to define the data transmission speed at the ADPCM interface.
Using these pins, the ADPCM data interface can be defined at a speed other than the PCM data
interface.
VDD
Power supply.
The device must operate between +2.7 V and +5.5 V.
PLCKEN
Input pin which enables the output of an 8 kHz clock from the PLLs.
This pin generates the internal master clocks. The 8 kHz clocks from the internal PLLs
synchronized with external signals applied to SYXA 1 - 4 are output to PLCK 1 - 4.
Set this pin at digital "0" during normal operation since it is used as the control pin for testing the
IC.
PLCK1 - 4
Output pins of the 8 kHz clock from PLLs.
When PLCKEN = "1", the 8 kHz clock pulses synchronized with external signals are applied to
SYXA1 - 4 outputs. When PLCKEN = "0", "0" level is output to these pins.
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