MSM7540L 데이터 시트보기 (PDF) - Oki Electric Industry

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MSM7540L

Single Rail ADPCM CODEC

Oki Electric Industry 

¡ Semiconductor

MSM7540L/7560L

SG

Analog signal ground voltage output.

The output voltage of this pin is approximately 1.4 V. Put bypass capacitors between this pin

and the AG pin. During power-down this output voltage is 0 V. The external SG voltage, if

necessary, should be used via a buffer.

AG

Analog ground.

DG

Digital ground.

This ground is separated internally from the analog signal ground pin (AG). The DG pin must

be kept as close as possible to AG on the PCB.

VDD

+3 V power supply.

LPS

PCM coding law selection.

MSM7540L only; if this pin goes to a "0" level, PCMSO, PCMSI, PCMRO, and PCMRI become the

A-law character signal, and if these pins goes to a "1" level, the signal becomes a linear value

character signal (2's complement).

MSM7560L only; if this pin goes to a "0" level, PCMSO, PCMSI, PCMRO, and PCMRI become the

m-law character signal, and if these pins goes to a "1" level, the signal becomes a linear value

character signal (2's complement).

PDN

Power down control input.

If this pin is "0", this device is in the power-down state.

Normally, this pin is set to "1".

RES

Optional reset input specified by ITU-T Recommendation G. 721.

If this pin is "0", the device is in the reset state. The reset width (during "L") should be 125 ms or

more.

MCK

Master clock input.

The frequency must be 10.368 MHz. The master clock signal may be asynchronous to BCLKA,

BCLKB, XSYNC, and RSYNC.

PCMSO

Transmit PCM data output.

PCM is output from MSB in synchronization with the rising edge of BCLKB and XSYNC.

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