MSM7540 데이터 시트보기 (PDF) - Oki Electric Industry

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MSM7540

Single Rail ADPCM CODEC

Oki Electric Industry 

¡ Semiconductor

MSM7540/7560

TIMING DIAGRAM

Transmit Side PCM/ADPCM Data Interface

BCLKB

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14

txs

tsx

tws

XSYNC

PCMSO

PCMSO

(during linear)

txd1 txd2

MSB

tsdx

MSB

txd3

LSB

txd3

LSB

BCLKA

0

1

2

3

4

5

6

7

8

9 10

txs

tsx

XSYNC

IS

txd1 txd2

tsdx MSB

txd3

LSB

Receive Side PCM/ADPCM Data Interface

BCLKA

0

1

2

3

4

5

67

8

9 10 11 12 13 14

trs

tsr

tws

RSYNC

tds

tdh

txd3

IR

MSB

LSB

BCLKB

0

trs

1

tsr

2

3

4

5

6

7

8

9 10

RSYNC

trd1 trd2

txd3

PCMRO

MSB

LSB

tsdx

PCMRO

MSB

(during linear)

Note: Linear format

trd3

LSB

A code of an input/output level is determined by the 14-bit 2'compliment.

Refer to the table below for code format.

Input/Output level

+Full-scall

0

–Full-scall

MSB to LSB

01111111111111

00000000000000

10000000000000

13/15

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