NJU6676CH 데이터 시트보기 (PDF) - Japan Radio Corporation

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NJU6676CH

64-Common X 132-Segment plus 1-Icon Bit Map Type LCD Controller and Driver

Japan Radio Corporation  

NJU6676

PRELIMINARY

b) Display data latch circuit

The display data latch circuit temporally stores 132-bit display data transferred from the DDRAM in

the synchronization with the common timing signal, and then it transfers these stored data to the

segment drivers.

“Display on/off”, “inverse display on/off” and “entire display on/off” instructions control only the

contents of this latch circuit, they can’t change the contents of the DDRAM.

In addition, the LCD display isn’t affected by the DDRAM accuses during its displaying because the

data read-out timing from this latch circuit to the segment drivers is independent of accessing timing

to the DDRAM.

c) Line counter and latch signal or latch Circuits

The clock line counter and latch signal to the latch circuits are generated from the internal display

clock (CL). The line address of display data RAM is renewed synchronizing with display clock (CL).

132bits display data are latched in display latch circuits synchronizing with display clock, and then

output to the LCD driving circuits. The display data transfer to the LCD driving circuits is executed

independently with RAM access by the MPU.

d) Display timing generator

The display timing generates the timing signal for the display system bay combination of the master

clock CL and driving signal FR ( refer to Fig.2 ) The frame signal FR and LCD alternative signal

generate LCD driving waveform on the two frame alternative driving method.

e) Common timing generation

The common timing is generated by display clock CL (refer to Fig.2)

Fig.2 Display Timing

64 63 1 2 3 4 5 6 7 8

CL

64 63 1 2 3 4 5 6 7 8

FR

COM0

COM1

RAM data

SEG n

Fig.2 Waveform of Display Timing

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