MSM10S0000 데이터 시트보기 (PDF) - Oki Electric Industry

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MSM10S0000

0.8 µm Sea of Gates Family 3-V and 5-V Applications

Oki Electric Industry 

s MSM10S0000 s ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

ARRAY ARCHITECTURE

The primary components of a 0.8 µm SOG circuit include:

• I/O base cells

• Configurable I/O pads for VDD, VSS, or I/O

• VDD and VSS pads dedicated to wafer probing

• Separate power bus for output buffers

• Separate power bus for internal core logic and input buffers

• Core base cells contain n-channel and p-channel pairs, arranged in column of gates

• Isolated gate structure for reduced input capacitance and increased routing flexibility

Each array has 16 dedicated corner pads for power and ground use during wafer probing. There are four

pads per corner. The arrays also have separate power rings for the internal core functions (VDDC and

VSSC) and the output drive transistors (VDDO and VSSO) as shown in Figure 1.

I/O base cells

Separate power bus (VDDC, VSSC) for

internal core logic and input buffers

Configurable I/O pads

for VDD, VSS, or I/O

Core base cell

with 4 transistors

VDD, VSS pads (4)

in each corner for

wafer probing only

Separate power bus (VDDO, VSSO)

over I/O cell for output buffers

Cell Width

24 mA

Output

Buffer

8 mA

Output

Buffer

16 mA

Output

Buffer

8 mA

Output

Buffer

I/O Base Cell

Wire Bond

Pitch

Bonding Pad

Figure 1. MSM10S0000 Array Architecture

2

Oki Semiconductor

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