6260G 데이터 시트보기 (PDF) - MOSA ELECTRONICS
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6260G Datasheet PDF : 11 Pages
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MOSA
MS6260
Gain And Attenuation Volume Controller IC
CAP=22uF
CAP=10uF
CAP=2.2uF
VDD=5V
VRR=-20dBV
FREQUENCY (Hz)
PSRR vs. frequency
CAP=22uF
CAP=10uF
CAP=2.2uF
VDD=3.3V
VRR=-20dBV
FREQUENCY (Hz)
PSRR vs. frequency
CAP=22uF
CAP=10uF
CAP=2.2uF
VDD=2.7V
VRR=-20dBV
FREQUENCY (Hz)
PSRR vs. frequency
I2C BUS DESCRIPTION
Start and stop conditions
A start condition is activated when the SCL is set to HIGH and SDA shifts from HIGH to LOW state. The stop
condition is activated when SCL is set to HIGH and SDA shifts from LOW to HIGH state. Please refer to the timing
diagram below.
SCL
SDA
Start
Stop
SCL : Serial Clock Line, SDA : Serial Data Line
Data validity
A data on the SDA line is considered valid and stable only when the SCL signal is in HIGH state. The HIGH and
LOW states of the SDA line can only change when the SCL signal is LOW. Please refer to the figure below.
SDA
SCL
Data line Data
stable, change
Data valid allowed
Byte format
Every byte transmitted to the SDA line consists of 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transmitted first.
REV 1
5
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