MPC948L 데이터 시트보기 (PDF) - Motorola => Freescale
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MPC948L Datasheet PDF : 6 Pages
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MPC948L
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
Max
Unit
VCC
VI
IIN
TStor
Supply Voltage
Input Voltage
Input Current
Storage Temperature Range
–0.3
4.6
V
–0.3
VDD + 0.3
V
±20
mA
–40
125
°C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.
DC CHARACTERISTICS (TA = 0° to 70°C, VCCI = 3.3V ±5%; VCCO = 2.5V ±5% or 3.3V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
VIH
Input HIGH Voltage
PECL_CLK
Other
2.135
2.0
2.42
V Single Ended Spec
3.60
VIL
Input LOW Voltage
PECL_CLK 1.49
Other
1.825
0.8
V Single Ended Spec
VPP
VCMR
VOH
Peak–to–Peak Input Voltage
Common Mode Range
Output HIGH Voltage
PECL_CLK
300
PECL_CLK
VCCO = 3.3V
VCCO = 2.5V
VCC – 2.0
2.5
2.0
1000
mV
VCC – 0.6 V
V
Note 1.
IOH = –20mA (Note 2.)
VOL
Output LOW Voltage
0.4
V
IOL = 20mA (Note 2.)
IIN
Input Current
±100
µA Note 3.
CIN
Input Capacitance
4
pF
Cpd
Power Dissipation Capacitance
25
pF Per Output
ICC
Maximum Quiescent Supply Current
22
30
mA
1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within
the VCMR range and the input swing lies within the VPP specification.
2. The MPC948L outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications
Info section).
3. Inputs have pull–up resistors which affect input current, PECL_CLK has a pull–down resistor.
AC CHARACTERISTICS (TA = 0° to 70°C, VCCI = 3.3V ±5%; VCCO = 2.5V ±5% or 3.3V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Fmax
tpd
Maximum Input Frequency
150
Propagation Delay
PECL_CLK to Q
7.0
TTL_CLK to Q
7.9
MHz
ns
tsk(o)
tsk(pr)
Output–to–Output Skew
Part–to–Part Skew
PECL_CLK to Q
TTL_CLK to Q
350
ps
1.5
ns
2.0
tpwo
Output Pulse Width
tCYCLE/2 –
800
tCYCLE/2+ ps
800
ts
Setup Time
Sync_OE to PECL_CLK
1.0
ns
Sync_OE to TTL_CLK
0.0
th
Hold Time
PECL_CLK to Sync_OE
0.0
ns
TTL_CLK to Sync_OE
1.0
tPZL,tPZH
Output Enable Time
3
tPLZ,tPHZ
Output Disable Time
3
tr, tf
Output Rise/Fall Time
0.20
4. Driving 50Ω transmission lines
5. Part–to–part skew at a given temperature and voltage
6. Assumes 50% input duty cycle.
7. Setup and Hold times are relative to the falling edge of the input clock
11
ns
11
ns
1.0
ns
Condition
Note 4.
Note 4.
Note 4.
Notes 4., 5.
Notes 4., 6.
Measured at VCC/2
Notes 4., 7.
Notes 4., 7.
0.8V to 2.0V
TIMING SOLUTIONS
3
BR1333 — Rev 6
MOTOROLA
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