MP7610
A0 to A15
MC6800
02
R/W
DBO to DB7
16
8
16 Address Bus
3
E1 A0 to A2
E3
74LS138
Address
E2 Decoder
8 Data Bus
LD
CLK
DB7 SDI
RST
From SYSTEM RESET
NOTES
1. Execute consecutive memory write instructions while manipulating the data between WRITEs so that each
WRITE presents the next bit.
2. The serial data loading is triggered by the CLK pulse which is asserted by a decoded memory WRITE to
memory location 2000, R/W, and 02. A WRITE to address 4000 transfers data from input shift register to DAC
register.
Figure 7. MC6800 Interface
8085
ALE
WR
SOD
8
Address Bus
8
8212
+5
8
Data Bus
3
E1 A0 to A2
E3
74LS138
Address
E2 Decoder
LD
SDI
CLK
RST
NOTES:
From SYSTEM RESET
1. Clock generated by WR and decoding address 8000.
2. Data is clocked in the DAC shift register by executing memory write instructions. The clock input is generated
by decoding address 8000 and WR. Data is then loaded into the DAC register with a memory write instruction
to address 4000.
3. Serial data must be present in the right justified format in registers H & L of the microprocessor.
Figure 8. 8085 Interface
Rev. 4.01
10