MP1232A 데이터 시트보기 (PDF) - Exar Corporation
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MP1232A
Exar Corporation
MP1232A Datasheet PDF : 12 Pages
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MP1230A/31A/32A
THEORY OF OPERATION
VDD VREF
DB11 (MSB) (DB3)
DB10 (DB2)
DB9 (DB1)
DB8 (DB0)
DB7
DB6
DB5
DB4
BYTE1/BYTE2
CS
WR1
XFER
WR2
D
Q
D
Q
D
Q
D 8-Bit Q
D Input Q
D Latch Q
D
Q
D LE Q
D 4-Bit Q
D Input Q
D Latch Q
D LE Q
When LE = 1, Q Outputs Follow D Inputs
When LE = 0, Q Outputs are Latched
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D 12-Bit Q
D DAC Q
Register
D
Q
D
Q
D
Q
D LE Q
DGND
MSB
12-Bit
Multiplying
D/A
Converter
LSB
AGND
RFB
IOUT1
IOUT2
Figure 1. Functional Diagram
Digital Interface
Figure 1. shows the internal control logic that controls the
writing of the input latches. It is easy to understand how the
MP1230A/31A/32A works by understanding each basic opera-
tion.
Writing to Input Latches
The condition BYTE1/BYTE2= high, CS = WR1 = 0 loads the
data bus DB11-DB4 into both input latches.
A second cycle with BYTE1/BYTE2 = low (Figure 2.) loads
the pins DB11-DB8 (DB3-DB0) into the 4-bit input latch.
Timing diagrams show the inputs CS and DB11-DB0 to be
stable during the entire writing cycle. In reality all the above sig-
nals can change (Figure 2.) as long as they meet the timing con-
ditions specified in the Electrical Characteristic Table.
CS
BYTE1/BYTE2
DATA
WR1
Transferring Data to the DAC Latches
Once one or all the input latches have been loaded, the condi-
tion XFER= WR2= low transfers the content of the input latches
in the DAC latch. The outputs of the DAC latch change and the
DAC current (IOUT) will reach a new stable value within the set-
tling time tS (Figure 3.).
XFER
WR2
DB11-0
or
or
IOUT
tS
Figure 3. Transfer Cycles from
Input Latches to DAC Latches
Figure 2. Write Cycles to Input Latches
Rev. 2.00
6
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