LP62E16256C-T 데이터 시트보기 (PDF) - AMIC Technology

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LP62E16256C-T

256K X 16 BIT LOW VOLTAGE CMOS SRAM

AMIC Technology 

AC Test Conditions

Input Pulse Levels

Input Rise And Fall Time

Input and Output Timing Reference Levels

Output Load

LP62E16256C-T Series

0.2V to Vcc -0.2V

5 ns

0.9V

See Figures 1 and 2

TTL

TTL

CL

30pF

CL

5pF

* Including scope and jig.

Figure 1. Output Load

Data Retention Characteristics (TA = -25°C to 85°C)

Symbol

Parameter

VDR

VCC for Data Retention

* Including scope and jig.

Figure 2. Output Load for tCLZ, tOLZ,

tCHZ, tOHZ, tWHZ, and tOW

Min.

1.2

Max. Unit

Conditions

2.2

V

CE ≥ VCC - 0.2V

ICCDR

Data Retention Current

-

5*

tCDR

Chip Disable to Data Retention Time

0

-

tR

Operation Recovery Time

tRC

-

tVR

VCC Rising Time from Data Retention

Voltage to Operating Voltage

5

-

* LP62E16256C-70LLT

* LP62E16256C-60LLT

ICCDR: max. 1µA at TA = 0°C to + 40°C

ICCDR: max. 1µA at TA = 0°C to + 40°C

VCC = 1.2V,

µA

CE ≥ VCC - 0.2V

VIN ≥ 0V

ns

ns

See Retention Waveform

ms

(August, 2001, Version 1.0)

11

AMIC Technology, Inc.

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