MM74HC86MX_NL 데이터 시트보기 (PDF) - Fairchild Semiconductor
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MM74HC86MX_NL Datasheet PDF : 7 Pages
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September 1983
Revised January 2005
MM74HC86
Quad 2-Input Exclusive OR Gate
General Description
The MM74HC86 EXCLUSIVE OR gate utilizes advanced
silicon-gate CMOS technology to achieve operating
speeds similar to equivalent LS-TTL gates while maintain-
ing the low power consumption and high noise immunity
characteristic of standard CMOS integrated circuits. These
gates are fully buffered and have a fanout of 10 LS-TTL
loads. The 74HC logic family is functionally as well as pin
out compatible with the standard 74LS logic family. All
inputs are protected from damage due to static discharge
by internal diode clamps to VCC and ground.
Features
s Typical propagation delay: 9 ns
s Wide operating voltage range: 2–6V
s Low input current: 1 µA maximum
s Low quiescent current: 20 µA maximum (74 Series)
s Output drive capability: 10 LS-TTL loads
Ordering Code:
Order Number
Package
Number
Package Description
MM74HC86M
M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC86MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC86SJ
M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC86MTC
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC86N
N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74HC86NX_NL
N14A Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Truth Table
Pin Assignments for DIP, SOIC, SOP and TSSOP
Inputs
A
B
L
L
L
H
H
L
H
H
Y = A ⊕ B = A B + AB
Outputs
Y
L
H
H
L
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© 2005 Fairchild Semiconductor Corporation DS005305
www.fairchildsemi.com
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