MM74C905 데이터 시트보기 (PDF) - Fairchild Semiconductor
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MM74C905 Datasheet PDF : 8 Pages
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Typical Applications
12-Bit Successive Approximation A-to-D Converter,
Operating in Continuous 8–Bit Truncated Mode
12-Bit Successive Approximation A-to-D Converter, Operating in
Continuous Mode, Drives the 50k/100k Ladder Network Directly
Definition of Terms
CP: Register clock input.
CC: Conversion complete—this output remains at VOUT(1)
during a conversion and goes to VOUT(0) when conversion
is complete.
D: Serial data input—connected to comparator output in A-
to-D applications.
E: Register enable —this input is used to expand the
length of the register. When E is at VIN(1) Q11 is forced to
VOUT(1) and inhibits conversion. When not used for expan-
sion E must be connected to VIN(0) (GND).
Q11: True register MSB output.
Q11: Complement of register MSB output.
Qi (i = 0 to 11): Register outputs.
S: Start input—holding start input at VIN(0) for at least one
clock period will initiate a conversion by setting MSB (Q11)
at VOUT(0) and all other output (Q10–Q0) at VOUT(1). If set-
up time requirements are met, a conversion may be initi-
ated by holding start input at VIN(0) for less than one clock
period.
DO: Serial data output—D input delayed by one clock
period.
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