ML7055 데이터 시트보기 (PDF) - Oki Electric Industry
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ML7055 Datasheet PDF : 30 Pages
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OKI Semiconductor
FEDL7055-02
ML7055
RF I/F
Pin Name
PLLLOCK
PLL_OFF
Direc-
tion
[*0]
I
O
Internal
Pull Up/
Down,
Schmitt
Pull
down
Initial
Value
—
—
—
Pin Placement
ML7055 ML7055 ML7055
HB
LA
LP
B4
B6
B5
H
—
—
D6
B1
B1
L
Description
ML7050: —
CX72303: —
BCM2002X: 1MHz clock
ML7050: PLL loop control
0: Open loop 1: Closed loop
CX72303: Diversity output
BCM2002X: PA Power control
PCM I/F
Pin Name Direc-
tion
Internal
Pull Up/
Down,
Schmitt
Initial
Value
Pin Placement
ML7055 ML7055 ML7055
HB
LA
LP
Description
PCMOUT O
—
L
G6
J3
J4 PCM data output
PCMIN
I
Pull up —
H4
J5
H5 PCM data input
PCM sync signal (8 kHz),
Pull
PCMSYNC I/O
down
—
F5
J4
K4
Initial setting: input
(can be switched by an internal
register)
PCM clock (64 kHz/128 kHz)
PCMCLK I/O
Pull
down
—
G5
K4
H4
Initial setting: input
(can be switched by an internal
register)
Note: The PCM sync signal (8 kHz) must be guaranteed at the accuracy of ±50 ppm if the
PCMSYNC pin is configured as an input.
UART I/F
Pin Name
Direc-
tion
SOUT
O
SIN
I
RTS
O
CTS
I
Internal
Pull Up/
Down,
Schmitt
—
Schmitt
—
—
Initial
Value
H
—
—
H
Pin Placement
ML7055
HB
E7
D4
G2
F3
ML7055
LA
F1
G1
J9
K9
ML7055
LP
F2
G2
K9
J9
Description
ACE transmit serial data
ACE receive serial data
ACE transmit data ready
ACE transmit ready
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