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ML7048

3-Channel Single Rail CODEC

Oki Electric Industry 

1Semiconductor

PEDL7048-01-01

ML7048-01

Cross-talk between Channels

This device contains a 3-channel CODEC.

The circuits and layout of this device have been designed so that the internal cross-talk between channels is to be as

small as possible. The pins also are carefully placed.

It is required to design your printed circuit board considering the following descriptions.

Transmit Side:

AN1+, AN1–, AIN2+, AIN2–, AIN3+, and AIN3– are the input pins for op-amps with a high resistance.

Consequently, if the wiring patterns of these pins are close to the wiring patterns of other signals, cross-talk

may be caused. And a longer wiring pattern generates noises.

The wiring pattern must be as short as possible and must not be close to the patterns of other signals. In addition,

connect a ground pattern between these wiring patterns and the wiring patterns of other signals.

AIN1+, AIN2+, and AIN3+ are connected to SGC.

Connect a bypass capacitor to the SGC pin as closely as possible and place a wiring pattern for AIN+, AIN2+,

and AIN3+ separately.

Receive Side:

AOUT1+, AOUT1–, AOUT2+, AOUT2–, AOUT3+, and AOUT3– are the outputs for op-amps with a low

resistance. Although the cross-talk caused by wiring patterns is small when compared with the transmit side,

Avoid placing the wiring patterns of these pins closely to the wiring patterns of other signals.

RSYNC Timing

Data that is input from DINn is latched at the rising edge of BCLK corresponding to the trailing edge of the last

bit.

If the latch timing and the internal processing timing (25.390 µs from the rise of XSYNC) are overlapped, data

slip (data is deleted or the same data is output twice) data error may occur.

Set the timing so that the latch timing and internal processing timing are not within ±500 ns considering the

jitter of DPLL.

XSYNC

RSYNC

BCLK

DINn

25.390 µs

Last bit

Latch timing

Internal processing

timing

Relationship between MCK and BCLK, XSYNC, RSYNC

Although MCK may be asynchronous with BCLK, XSYNC, and RSYNC, take note of the following.

If MCK and BCLK, XSYNC, RSYNC are generated from the different oscillation sources (ex. two crystal

oscillators are used) with the same frequency, the difference in frequency may cause a beat. If this beat frequency

is within the band, the characteristics may be degraded.

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