ML7033 데이터 시트보기 (PDF) - Oki Electric Industry

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ML7033

Dual-Channel Line Card CODEC

Oki Electric Industry 

1Semiconductor

FEDL7033-02

ML7033

Table 4 State of PCMOUT in 14-bit Linear PCM Mode with LIN (CR0-B3) bit = “1”

PDN pin

0

1

1

1

1

MODE1 bit

0/1

0

0

1

1

MODE0 bit

0/1

0

1

0

1

ALAW bit

0/1

CH2 PCM Data

Hi-Z *1

ALL “0”

ALL “0”

Operate

Operate

CH1 PCM Data

Hi-Z *1

ALL “0”

Operate

ALL “0”

Operate

Table 5 State of Analog Output Pins

PDN MODE1 MODE0 GSX1

pin bit

bit

pin

0

0/1

0/1

Hi-Z

1

0

0

Hi-Z

1

0

1 Operate

1

1

0

Hi-Z

1

1

1 Operate

GSX2

pin

Hi-Z

Hi-Z

Hi-Z

Operate

Operate

AOUT1

pin

Hi-Z

Hi-Z

Operate

Hi-Z

Operate

AOUT2

pin

Hi-Z

Hi-Z

Hi-Z

Operate

Operate

SG

pin

Hi-Z

Hi-Z

Operate

Operate

Operate

SGC

pin

AG level *2

AG level *2

Operate

Operate

Operate

MCU

Interface

Operate

Operate

Operate

Operate

Operate

*1 The data will be ‘H’ by an external pull-up resistor.

*2 Output impedance = about 50 kΩ

F2_1, F1_1, F0_1, F2_2, F1_2, F0_2

The F2_n, F1_n and F0_n pins are data outputs used when the SLIC connected to the corresponding channel is

an Intersil RSLICTM series device. The output levels from the F2_n, the F1_n and F0_n pins are determined by

the F2_n, F1_n, and F0_n register bits (CR6-B7 to B5 and CR13-B7 to B5). By inputting these outputs directly

into the corresponding input pin of the SLIC device, the SLIC operating mode selection is possible.

Even in the power-down state with the PDN pin is asserted, these pins remain functional.

E0_1, E0_2

The E0_n pins are the detector mode selection data outputs. These pins are used when the SLIC connected to the

corresponding channel is an Intersil RSLICTM series device. Though the output level from the E0_n pin is

determined by the E0_n bit (CR6-B2/CR13-B2), the output level changes in 20 µs (= hold timer) in the power-

on mode with the PDN pin = logic “1” and in 200 ns in the power-down mode with the PDN pin = logic “0”

after the change of E0_n bit (CR6-B2 /CR13-B2). Refer to Figure 6 for information.

What event is actually detected by the SLIC is determined by the combination of the F2_n, F1_n, F0_n and E0_n

pins. Refer to Table 6 for more information. By connecting the output directly into the corresponding input pin

of the SLIC device, detector mode selection in the SLIC is possible. Even in the power-down state with the PDN

pin = logic “0”, this pin remains functional. However, the hold timer is ignored in this state.

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