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MDS108AL

Unmanaged 9-Port 10/100 Mbps Ethernet Switch

Zarlink Semiconductor Inc 

MDS108

Unmanaged 9-Port 10/100 Mbps

Ethernet Switch

Data Sheet

Features

• 8 10/100 Mbps auto-negotiating RMII ports

• 1 10/100 Mbps auto-negotiating MII/serial port

(port 8) that can be used as a WAN uplink or as a

9th port

• Operates stand-alone or can be cascaded with a

second MDS108 to reach 16 ports

- XLink expansion MII port (port 8)

- Operates at 100/200/300/400 Mbps

• External I2C EEPROM for power-up configuration

- Default mode allows operation without external

EEPROM

• Up to 8 port-based VLANs

• Full wirespeed layer 2 switching on all ports (up to

2.679 M packets per second)

• Internal 1 K MAC address table

- Auto address learning

- Auto address aging

• Leading-edge Quality of Service (QoS)

capabilities provided based on 802.1 p and IP

TOS/DS field

- 2 queues per output port

- Packet scheduling based on Weighted Round

Robin (WRR) and Weighted Random Early

Detection/Drop (WRED)

- With flow control disabled, can drop packets

during congestion using WRED

- 2 levels of packet drop provided

• Provides port-based prioritization of packets on

up to 4 ports

November 2003

Ordering Information

MDS108AL 208 Pin PQFP

-40°C to +85°C

- Input ports are defined to be high or low priority

- Allows explicit identification of IP phone ports

• Supports both full and half duplex ports

• Ports 0 & 1 can be trunked to provide a 200 Mbps

link to another switch or server

• Port 7 can be used to mirror traffic from the other 7

ports (0-6)

• Utilizes a single low-cost external pipelined,

SyncBurst SRAM (SBRAM) for buffer memory

- 256 KB or 512 KB (1 chip)

• Flow control capabilities

- Provides back-pressure for half duplex

- 802.3x flow control for full duplex

• Supports external parallel port for configuration

updates

• Special power-saving mode for inactive ports

• Ability to support WinSock 2.0 and Windows2000

smart applications

• Transmit delay control capabilities

- Assures maximum delay (< 1 ms)

- Supports mixed voice/data networks

• Optimized pin-out for easy board layout

Figure 1 - System Block Diagram

1

Zarlink Semiconductor Inc.

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Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.

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