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MC74HC165A

8−Bit Serial or Parallel−Input/ Serial−Output Shift Register

ON Semiconductor 

MC74HC165A

PIN DESCRIPTIONS

INPUTS

A, B, C, D, E, F, G, H (Pins 11, 12, 13, 14, 3, 4, 5, 6)

Parallel Data inputs. Data on these inputs are

asynchronously entered in parallel into the internal

flip−flops when the Serial Shift/Parallel Load input is low.

SA (Pin 10)

Serial Data input. When the Serial Shift/Parallel Load

input is high, data on this pin is serially entered into the first

stage of the shift register with the rising edge of the Clock.

CONTROL INPUTS

Serial Shift/Parallel Load (Pin 1)

Data−entry control input. When a high level is applied to

this pin, data at the Serial Data input (SA) are shifted into the

register with the rising edge of the Clock. When a low level

is applied to this pin, data at the Parallel Data inputs are

asynchronously loaded into each of the eight internal stages.

Clock, Clock Inhibit (Pins 2, 15)

Clock inputs. These two clock inputs function identically.

Either may be used as an active−high clock inhibit.

However, to avoid double clocking, the inhibit input should

go high only while the clock input is high.

The shift register is completely static, allowing Clock

rates down to DC in a continuous or intermittent mode.

OUTPUTS

QH, QH (Pins 9, 7)

Complementary Shift Register outputs. These pins are the

noninverted and inverted outputs of the eighth stage of the

shift register.

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