MC74HC164AN 데이터 시트보기 (PDF) - ON Semiconductor
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MC74HC164AN Datasheet PDF : 11 Pages
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MC74HC164A
PIN DESCRIPTIONS
INPUTS
A1, A2 (Pins 1, 2)
Serial Data Inputs. Data at these inputs determine the data
to be entered into the first stage of the shift register. For a
high level to be entered into the shift register, both A1 and
A2 inputs must be high, thereby allowing one input to be
used as a data−enable input. When only one serial input is
used, the other must be connected to VCC.
Clock (Pin 8)
Shift Register Clock. A positive−going transition on this
pin shifts the data at each stage to the next stage. The shift
register is completely static, allowing clock rates down to
DC in a continuous or intermittent mode.
OUTPUTS
QA − QH (Pins 3, 4, 5, 6, 10, 11, 12, 13)
Parallel Shift Register Outputs. The shifted data is
presented at these outputs in true, or noninverted, form.
CONTROL INPUT
Reset (Pin 9)
Active−Low, Asynchronous Reset Input. A low voltage
applied to this input resets all internal flip−flops and sets
Outputs QA − QH to the low level state.
SWITCHING WAVEFORMS
tr
tf
90%
VCC
CLOCK
50%
10%
GND
tw
90%
Q 50%
10%
1/fmax
tPLH
tPHL
tTLH
tTHL
tw
RESET
50%
VCC
GND
tPHL
Q
50%
CLOCK
trec
VCC
50%
GND
Figure 1.
Figure 2.
VALID
VCC
A1 OR A2
50%
GND
tsu
th
VCC
CLOCK
50%
GND
Figure 3.
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
*Includes all probe and jig capacitance
Figure 4. Test Circuit
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