MC74ACT564 데이터 시트보기 (PDF) - ON Semiconductor
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MC74ACT564 Datasheet PDF : 8 Pages
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MC74ACT564
D0
D1
D2
D3
D4
D5
D6
D7
CP
CD
Q
CD
Q
CD
Q
CD
Q
CD
Q
CD
Q
CD
Q
C
D
Q
OE
O0
O1
O2
O3
O4
O5
O6
O7
Please note that this diagram is provided only for the understanding of
logic operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
FUNCTION TABLE
Inputs
OE CP D
Internal Outputs
Q
O
Function
H
H
L
NC
Z
Hold
H
H
H
NC
Z
Hold
H
L
H
Z
Load
H
H
L
Z
Load
L
L
H
H
Data Available
L
H
L
L
Data Available
L
H
L
NC
NC No Change in Data
L
H
H
NC
NC No Change in Data
H=
L=
X=
Z=
=
NC =
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
LOW−to−HIGH Transition
No Change
FUNCTIONAL DESCRIPTION
The MC74ACT564 consists of eight edge−triggered
flip−flops with individual D−type inputs and 3−state
complementary outputs. The buffered clock and buffered
Output Enable are common to all flip−flops. The eight
flip−flops will store the state of their individual D inputs that
meet the setup and hold times requirements on the
LOW−to−HIGH Clock (CP) transition. With the Output
Enable (OE) LOW, the contents of the eight flip−flops are
available at the outputs. When OE is HIGH, the outputs go
to the high impedance state. Operation of the OE input does
not affect the state of the flip−flops.
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