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MC33363BDWR2G Datasheet PDF : 11 Pages
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MC33363B
OPERATING DESCRIPTION
Introduction
The MC33363B represents a new higher level of
integration by providing all the active high voltage power,
control, and protection circuitry required for
implementation of a flyback or forward converter on a single
monolithic chip. This device is designed for direct operation
from a rectified 240 Vac line source and requires a minimum
number of external components to implement a complete
converter. A description of each of the functional blocks is
given below, and the representative block and timing
diagrams are shown in Figures 19, 18 and 20.
Oscillator and Current Mirror
The oscillator frequency is controlled by the values
selected for the timing components RT and CT. Resistor RT
programs the oscillator charge/discharge current via the
Current Mirror 4 I output, Figure 4. Capacitor CT is charged
and discharged by an equal magnitude internal current
source and sink. This generates a symmetrical 50 percent
duty cycle waveform at Pin 7, with a peak and valley
threshold of 2.6 V and 0.6 V respectively. During the
discharge of CT, the oscillator generates an internal blanking
pulse that holds the inverting input of the AND gate Driver
high. This causes the Power Switch gate drive to be held in
a low state, thus producing a well controlled amount of
output deadtime. The amount of deadtime is relatively
constant with respect to the oscillator frequency when
operating below 1.0 MHz. The maximum Power Switch
duty cycle at Pin 16 can be modified from the internal 50%
limit by providing an additional charge or discharge current
path to CT, Figure 21. In order to increase the maximum duty
cycle, a discharge current resistor RD is connected from
Pin 7 to ground. To decrease the maximum duty cycle, a
charge current resistor RC is connected from Pin 7 to the
Regulator Output. Figure 5 shows an obtainable range of
maximum output duty cycle versus the ratio of either RC or
RD with respect to RT.
Regulator Output
1.0 8
I
RC
6
RT
CT 7
RD
Current
Mirror
2.25 I
Current
Limit
Reference
4I
Oscillator
Blanking
Pulse
PWM
Comparator
Figure 21. Maximum Duty Cycle Modification
The formula for the charge/discharge current along with
the oscillator frequency are given below. The frequency
formula is a first order approximation and is accurate for CT
values greater than 500 pF. For smaller values of CT, refer
to Figure 2. Note that resistor RT also programs the Current
Limit Comparator threshold.
5.4
Ichg∕dscg = RT
f
≈
Ichg∕dscg
4CT
PWM Comparator and Latch
The pulse width modulator consists of a comparator with
the oscillator ramp voltage applied to the non--inverting input,
while the error amplifier output is applied into the inverting
input. The Oscillator applies a set pulse to the PWM Latch
while CT is discharging, and upon reaching the valley voltage,
Power Switch conduction is initiated. When CT charges to a
voltage that exceeds the error amplifier output, the PWM
Latch is reset, thus terminating Power Switch conduction for
the duration of the oscillator ramp--up period. This
PWM Comparator/Latch combination prevents multiple
output pulses during a given oscillator clock cycle. The
timing diagram shown in Figure 18 illustrates the Power
Switch duty cycle behavior versus the Compensation voltage.
Current Limit Comparator and Power Switch
The MC33363B uses cycle--by--cycle current limiting as a
means of protecting the output switch transistor from
overstress. Each on--cycle is treated as a separate situation.
Current limiting is implemented by monitoring the output
switch current buildup during conduction, and upon sensing
an overcurrent condition, immediately turning off the switch
for the duration of the oscillator ramp--up period.
The Power Switch is constructed as a SENSEFET allowing
a virtually lossless method of monitoring the drain current. It
consists of a total of 1462 cells, of which 36 are connected to
a 8.1 Ω ground--referenced sense resistor. The Current Sense
Comparator detects if the voltage across the sense resistor
exceeds the reference level that is present at the inverting
input. If exceeded, the comparator quickly resets the PWM
Latch, thus protecting the Power Switch. The current limit
reference level is generated by the 2.25 I output of the Current
Mirror. This current causes a reference voltage to appear
across the 405 Ω resistor. This voltage level, as well as the
Oscillator charge/discharge current are both set by resistor RT.
Therefore when selecting the values for RT and CT, RT must
be chosen first to set the Power Switch peak drain current,
while CT is chosen second to set the desired Oscillator
frequency. A graph of the Power Switch peak drain current
versus RT is shown in Figure 3 with the related formula
below.
Ipk = 8.8
RT --
1000 1.077
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