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MC14553BDW

3-Digit BCD Counter

ON Semiconductor 

MC14553B

3−Digit BCD Counter

The MC14553B 3−digit BCD counter consists of 3 negative edge

triggered BCD counters that are cascaded synchronously. A quad latch

at the output of each counter permits storage of any given count. The

information is then time division multiplexed, providing one BCD

number or digit at a time. Digit select outputs provide display control.

All outputs are TTL compatible.

An on−chip oscillator provides the low−frequency scanning clock

which drives the multiplexer output selector.

This device is used in instrumentation counters, clock displays,

digital panel meters, and as a building block for general logic

applications.

Features

• TTL Compatible Outputs

• On−Chip Oscillator

• Cascadable

• Clock Disable Input

• Pulse Shaping Permits Very Slow Rise Times on Input Clock

• Output Latches

• Master Reset

• Pb−Free Packages are Available*

MAXIMUM RATINGS (Voltages Referenced to VSS)

Parameter

Symbol

Value

Unit

DC Supply Voltage Range

Input or Output Voltage Range

(DC or Transient)

VDD −0.5 to +18.0 V

Vin,

−0.5 to VDD V

Vout

+ 0.5

Input Current (DC or Transient) per Pin

Iin

Output Current (DC or Transient) per Pin

Iout

±10

mA

+20

mA

Power Dissipation, per Package (Note 1)

PD

500

mW

Ambient Temperature Range

TA

−55 to +125 °C

Storage Temperature Range

Tstg −65 to +150 °C

Lead Temperature (8−Second Soldering)

TL

260

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating: Plastic “P and D/DW”

Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, Vin and Vout should be constrained to

the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either VSS or VDD). Unused outputs must be left open.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

© Semiconductor Components Industries, LLC, 2006

1

June, 2006 − Rev. 7

http://onsemi.com

MARKING

DIAGRAMS

PDIP−16 16

P SUFFIX

CASE 648

1

MC14553BCP

AWLYYWWG

1

16

SO−16W

DW SUFFIX

1

CASE 751G

MC14553B

AWLYYWW

1

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G = Pb−Free Package

4

3

CIA CIB Q0

9

12

CLOCK

Q1

7

10

LE

11

DIS

Q2

6

Q3

5

O.F.

14

DS1

2

13

MR

DS2

1

DS3

15

VDD = PIN 16

VSS = PIN 8

Figure 1. Block Diagram

ORDERING INFORMATION

Device

MC14553BCP

MC14553BCPG

MC14553BDW

Package

PDIP−16

PDIP−16

(Pb−Free)

SOIC−16

Shipping

25 Units / Rail

25 Units / Rail

47 Units / Rail

Publication Order Number:

MC14553B/D

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