MC14554 데이터 시트보기 (PDF) - Motorola => Freescale

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MC14554

2-Bit by 2-Bit Parallel Binary Multiplier

Motorola => Freescale 

Y(n–1)

M(n–2)

M(n–1)

Y(n–1)

EXPANSION DIAGRAM

m–Bit by n–Bit Parallel Binary Multiplier (Top View)

Y AND M

Y3

Y(n–2)

M2

X0

M3

X1

Y3

Y(n–2)

X2

X3

Y1 Y1 VDD

Y2

M0 M0 Y0 Y0

X0

M1 M1 X0 X0

X1

C0 X1 X1

M2 K0 K0

C1 S0

S2 K1 K1

VSS S1

Y1

Y2

Y0

X2

X2

X3

X3

K2

K3

X AND K

Y(n–1)

Y3

Y(n–2)

X(m–2)

X(m–1)

Y1

Y2

X(m–2)

X(m–1)

Y0

X(m–2)

X(m–1)

K(m–2)

K(m–1)

S(m + n–1) S(m + n–2)

S(m + n–3) S(m+2)

S(m+1)

S(m)

S(m–1) S3 S1

S(m–2) S2 S0

S = (X x Y) + K + M Where: x means Arithmetic Times.

S = (X x Y) + K + M Where: + means Arithmetic Plus.

S = S(m + n–1) S(m + n–2) … S2 S1 S0

X = X(m–1) X (m–2) … X2 X1 X0, Y = Y(n–1) Y(n–2) … Y2 Y1 Y0

K = K(m–1) K(m–2) … K2 K1 K0 and M = M(n–1) M(n–2) … M2 M1 M0

(Binary Numbers).

Number of output binary digits = m + n

Number of packages = mxn/4 (For m or n of both odd select next highest even number.)

MC14554B

4

MOTOROLA CMOS LOGIC DATA

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